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Update (2022.09.03) (openjdk#3)
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23864: Fix caller saved fpu regset
27580: Delete MIPS instructions in LA files
26659: Fix push_fpu/pop_fpu typo and implement push_vp/pop_vp to save/restore vector register
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@loongson-jvm
loongson-jvm authored Sep 3, 2022
1 parent 57e68ca commit e45ae0f
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Showing 11 changed files with 148 additions and 160 deletions.
1 change: 0 additions & 1 deletion src/hotspot/cpu/loongarch/assembler_loongarch.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1609,7 +1609,6 @@ class Assembler : public AbstractAssembler {
static int get_vec_imm(float x);
static int get_vec_imm(double x);

// LoongArch lui is sign extended, so if you wan't to use imm, you have to use the follow
static int split_low16(int x) {
return (x & 0xffff);
}
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8 changes: 4 additions & 4 deletions src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -428,10 +428,10 @@ void G1BarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler*
__ b(done);

__ bind(runtime);
__ pushad();
__ push_call_clobbered_registers();
__ load_parameter(0, pre_val);
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_pre_entry), pre_val, TREG);
__ popad();
__ pop_call_clobbered_registers();
__ bind(done);

__ epilogue();
Expand Down Expand Up @@ -496,9 +496,9 @@ void G1BarrierSetAssembler::generate_c1_post_barrier_runtime_stub(StubAssembler*
__ b(done);

__ bind(runtime);
__ pushad();
__ push_call_clobbered_registers();
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_post_entry), card_addr, TREG);
__ popad();
__ pop_call_clobbered_registers();
__ bind(done);
__ epilogue();
}
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20 changes: 10 additions & 10 deletions src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp
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Expand Up @@ -285,7 +285,7 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
__ beqz(SCR2, not_cset);
}

__ pushad_except_v0();
__ push_call_clobbered_registers_except(RegSet::of(V0));
if (is_strong) {
if (is_narrow) {
__ li(RA, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
Expand All @@ -304,7 +304,7 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
__ li(RA, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom));
}
__ jalr(RA);
__ popad_except_v0();
__ pop_call_clobbered_registers_except(RegSet::of(V0));

__ bind(not_cset);

Expand All @@ -320,9 +320,9 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,

void ShenandoahBarrierSetAssembler::iu_barrier(MacroAssembler* masm, Register dst, Register tmp) {
if (ShenandoahIUBarrier) {
__ pushad();
__ push_call_clobbered_registers();
satb_write_barrier_pre(masm, noreg, dst, TREG, tmp, true, false);
__ popad();
__ pop_call_clobbered_registers();
}
}

Expand Down Expand Up @@ -374,15 +374,15 @@ void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet d
// 3: apply keep-alive barrier if needed
if (ShenandoahBarrierSet::need_keep_alive_barrier(decorators, type)) {
__ enter();
__ pushad();
__ push_call_clobbered_registers();
satb_write_barrier_pre(masm /* masm */,
noreg /* obj */,
dst /* pre_val */,
TREG /* thread */,
tmp1 /* tmp */,
true /* tosca_live */,
true /* expand_call */);
__ popad();
__ pop_call_clobbered_registers();
__ leave();
}
}
Expand Down Expand Up @@ -729,10 +729,10 @@ void ShenandoahBarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAss
__ b(done);

__ bind(runtime);
__ pushad();
__ push_call_clobbered_registers();
__ load_parameter(0, pre_val);
__ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), pre_val, thread);
__ popad();
__ pop_call_clobbered_registers();
__ bind(done);

__ epilogue();
Expand All @@ -743,7 +743,7 @@ void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_s
__ bstrins_d(SP, R0, 3, 0);
// arg0 : object to be resolved

__ pushad_except_v0();
__ push_call_clobbered_registers_except(RegSet::of(V0));
__ load_parameter(0, A0);
__ load_parameter(1, A1);

Expand Down Expand Up @@ -774,7 +774,7 @@ void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_s
__ li(RA, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom));
}
__ jalr(RA);
__ popad_except_v0();
__ pop_call_clobbered_registers_except(RegSet::of(V0));

__ epilogue();
}
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27 changes: 20 additions & 7 deletions src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -99,15 +99,15 @@ void ZBarrierSetAssembler::load_at(MacroAssembler* masm,
if (dst != V0) {
__ push(V0);
}
__ pushad_except_v0();
__ push_call_clobbered_registers_except(RegSet::of(V0));

if (dst != A0) {
__ move(A0, dst);
}
__ move(A1, scratch);
__ MacroAssembler::call_VM_leaf_base(ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr(decorators), 2);

__ popad_except_v0();
__ pop_call_clobbered_registers_except(RegSet::of(V0));

// Make sure dst has the return value.
if (dst != V0) {
Expand Down Expand Up @@ -290,15 +290,15 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_runtime_stub(StubAssembler*
DecoratorSet decorators) const {
__ prologue("zgc_load_barrier stub", false);

__ pushad_except_v0();
__ push_call_clobbered_registers_except(RegSet::of(V0));

// Setup arguments
__ load_parameter(0, A0);
__ load_parameter(1, A1);

__ call_VM_leaf(ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr(decorators), 2);

__ popad_except_v0();
__ pop_call_clobbered_registers_except(RegSet::of(V0));

__ epilogue();
}
Expand Down Expand Up @@ -327,6 +327,8 @@ class ZSaveLiveRegisters {
MacroAssembler* const _masm;
RegSet _gp_regs;
FloatRegSet _fp_regs;
FloatRegSet _lsx_vp_regs;
FloatRegSet _lasx_vp_regs;

public:
void initialize(ZLoadBarrierStubC2* stub) {
Expand All @@ -339,32 +341,43 @@ class ZSaveLiveRegisters {
if (vm_reg->is_Register()) {
_gp_regs += RegSet::of(vm_reg->as_Register());
} else if (vm_reg->is_FloatRegister()) {
_fp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
if (UseLASX && vm_reg->next(7))
_lasx_vp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
else if (UseLSX && vm_reg->next(3))
_lsx_vp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
else
_fp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
} else {
fatal("Unknown register type");
}
}
}

// Remove C-ABI SOE registers, scratch regs and _ref register that will be updated
_gp_regs -= RegSet::range(r23, r30) + RegSet::of(r3, r16, r19, stub->ref());
_gp_regs -= RegSet::range(S0, S7) + RegSet::of(SP, SCR1, SCR2, stub->ref());
}

ZSaveLiveRegisters(MacroAssembler* masm, ZLoadBarrierStubC2* stub) :
_masm(masm),
_gp_regs(),
_fp_regs() {
_fp_regs(),
_lsx_vp_regs(),
_lasx_vp_regs() {

// Figure out what registers to save/restore
initialize(stub);

// Save registers
__ push(_gp_regs);
__ push_fpu(_fp_regs);
__ push_vp(_lsx_vp_regs /* UseLSX */);
__ push_vp(_lasx_vp_regs /* UseLASX */);
}

~ZSaveLiveRegisters() {
// Restore registers
__ pop_vp(_lasx_vp_regs /* UseLASX */);
__ pop_vp(_lsx_vp_regs /* UseLSX */);
__ pop_fpu(_fp_regs);
__ pop(_gp_regs);
}
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12 changes: 6 additions & 6 deletions src/hotspot/cpu/loongarch/loongarch_64.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -8895,7 +8895,7 @@ instruct addI_salI_Reg_Reg_immI_1_4(mRegI dst, mRegI src1, mRegI src2, immI_1_4
instruct addP_reg_reg(mRegP dst, mRegP src1, mRegLorI2L src2) %{
match(Set dst (AddP src1 src2));

format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
format %{ "ADD $dst, $src1, $src2 #@addP_reg_reg" %}

ins_encode %{
Register dst = $dst$$Register;
Expand All @@ -8910,7 +8910,7 @@ instruct addP_reg_reg(mRegP dst, mRegP src1, mRegLorI2L src2) %{
instruct addP_reg_imm12(mRegP dst, mRegP src1, immL12 src2) %{
match(Set dst (AddP src1 src2));

format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm12" %}
format %{ "ADD $dst, $src1, $src2 #@addP_reg_imm12" %}
ins_encode %{
Register src1 = $src1$$Register;
long src2 = $src2$$constant;
Expand Down Expand Up @@ -10920,7 +10920,7 @@ instruct CallLeafNoFPDirect(method meth) %{
instruct prefetchAlloc(memory mem) %{
match(PrefetchAllocation mem);
ins_cost(125);
format %{ "pref $mem\t# Prefetch allocation @ prefetchAlloc" %}
format %{ "preld $mem\t# Prefetch allocation @ prefetchAlloc" %}
ins_encode %{
int base = $mem$$base;
int index = $mem$$index;
Expand Down Expand Up @@ -11238,7 +11238,7 @@ instruct loadSSF(regF dst, stackSlotF src)
match(Set dst src);

ins_cost(125);
format %{ "lwc1 $dst, $src\t# float stk @ loadSSF" %}
format %{ "fld_s $dst, $src\t# float stk @ loadSSF" %}
ins_encode %{
guarantee( Assembler::is_simm($src$$disp, 12), "disp too long (loadSSF) !");
__ fld_s($dst$$FloatRegister, SP, $src$$disp);
Expand All @@ -11251,7 +11251,7 @@ instruct storeSSF(stackSlotF dst, regF src)
match(Set dst src);

ins_cost(100);
format %{ "swc1 $dst, $src\t# float stk @ storeSSF" %}
format %{ "fst_s $dst, $src\t# float stk @ storeSSF" %}
ins_encode %{
guarantee( Assembler::is_simm($dst$$disp, 12), "disp too long (storeSSF) !");
__ fst_s($src$$FloatRegister, SP, $dst$$disp);
Expand All @@ -11265,7 +11265,7 @@ instruct loadSSD(regD dst, stackSlotD src)
match(Set dst src);

ins_cost(125);
format %{ "ldc1 $dst, $src\t# double stk @ loadSSD" %}
format %{ "fld_d $dst, $src\t# double stk @ loadSSD" %}
ins_encode %{
guarantee( Assembler::is_simm($src$$disp, 12), "disp too long (loadSSD) !");
__ fld_d($dst$$FloatRegister, SP, $src$$disp);
Expand Down
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