Merge branch 'dev'

.gitignore

@@ -1,6 +1,201 @@
+# Created by https://www.toptal.com/developers/gitignore/api/python,modelsim
+# Edit at https://www.toptal.com/developers/gitignore?templates=python,modelsim
+
+### ModelSim ###
+# ignore ModelSim generated files and directories (temp files and so on)
+[_@]*
+
+# ignore compilation output of ModelSim
+*.mti
+*.dat
+*.dbs
+*.psm
+*.bak
+*.cmp
+*.jpg
+*.html
+*.bsf
+
+# ignore simulation output of ModelSim
+wlf*
+*.wlf
+*.vstf
+*.ucdb
+cov*/
+transcript*
+sc_dpiheader.h
+vsim.dbg
+
+### Python ###
 # Byte-compiled / optimized / DLL files
 __pycache__/
 *.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+share/python-wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+MANIFEST
+
+# PyInstaller
+#  Usually these files are written by a python script from a template
+#  before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.nox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*.cover
+*.py,cover
+.hypothesis/
+.pytest_cache/
+cover/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+db.sqlite3
+db.sqlite3-journal
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+.pybuilder/
+target/
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# IPython
+profile_default/
+ipython_config.py
+
+# pyenv
+#   For a library or package, you might want to ignore these files since the code is
+#   intended to run in multiple environments; otherwise, check them in:
+# .python-version
+
+# pipenv
+#   According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
+#   However, in case of collaboration, if having platform-specific dependencies or dependencies
+#   having no cross-platform support, pipenv may install dependencies that don't work, or not
+#   install all needed dependencies.
+#Pipfile.lock
+
+# poetry
+#   Similar to Pipfile.lock, it is generally recommended to include poetry.lock in version control.
+#   This is especially recommended for binary packages to ensure reproducibility, and is more
+#   commonly ignored for libraries.
+#   https://python-poetry.org/docs/basic-usage/#commit-your-poetrylock-file-to-version-control
+#poetry.lock
+
+# pdm
+#   Similar to Pipfile.lock, it is generally recommended to include pdm.lock in version control.
+#pdm.lock
+#   pdm stores project-wide configurations in .pdm.toml, but it is recommended to not include it
+#   in version control.
+#   https://pdm.fming.dev/#use-with-ide
+.pdm.toml
+
+# PEP 582; used by e.g. github.com/David-OConnor/pyflow and github.com/pdm-project/pdm
+__pypackages__/
+
+# Celery stuff
+celerybeat-schedule
+celerybeat.pid
+
+# SageMath parsed files
+*.sage.py
+
+# Environments
+.env
+.venv
+env/
+venv/
+ENV/
+env.bak/
+venv.bak/
+
+# Spyder project settings
+.spyderproject
+.spyproject
+
+# Rope project settings
+.ropeproject
+
+# mkdocs documentation
+/site
+
+# mypy
+.mypy_cache/
+.dmypy.json
+dmypy.json
+
+# Pyre type checker
+.pyre/
+
+# pytype static type analyzer
+.pytype/
+
+# Cython debug symbols
+cython_debug/
+
+# PyCharm
+#  JetBrains specific template is maintained in a separate JetBrains.gitignore that can
+#  be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore
+#  and can be added to the global gitignore or merged into this file.  For a more nuclear
+#  option (not recommended) you can uncomment the following to ignore the entire idea folder.
+#.idea/
+
+### Python Patch ###
+# Poetry local configuration file - https://python-poetry.org/docs/configuration/#local-configuration
+poetry.toml
+
+# ruff
+.ruff_cache/
+
+# End of https://www.toptal.com/developers/gitignore/api/python,modelsim
 
 # Temporary files created by the program
 /temp
@@ -20,10 +215,6 @@ __pycache__/
 # All zip files
 *.zip
 
-# ModelSim temporary files
-transcript
-*_out.tcl
-*.wlf
-*.mti
 # Not sure why this is here.
 Modelsim_tb 21/Lab6/vga_output.txt
+

grader.py

@@ -5,7 +5,8 @@
 import argparse
 import csv
 from pathlib import Path
-from scripts import extract_submissions, generate_tcl, StudentData
+from scripts import extract_submissions, generate_tcl, StudentData, run_simulations
+from shutil import which
 
 # ----------------------------------------------------------
 #                           METHODS
@@ -32,13 +33,22 @@ def read_student_text(text_file):
 def generate_tcl_mpf_filenames(lab_num: int):
     """Given a lab number, generate the filepaths 
     to relevant tcl files and modelsim project files."""
-    lab = "Lab{}".format(lab_num)
+    lab = "lab{}".format(lab_num)
     project_mpf = "modelsim-projects/Lab{}/Lab{}.mpf".format(lab_num, lab_num)
     tcl_file = "tcl-templates/lab{}.tcl".format(lab_num)
     tcl_out_file = "modelsim-projects/Lab{}/Lab{}_out.tcl".format(lab_num, lab_num)
 
     return lab, Path(project_mpf), Path(tcl_file), Path(tcl_out_file)
 
+def check_vsim_command():
+    """Verify that `vsim` is an operable command.
+    Otherwise, the tool will crash."""
+    if which("vsim") is None:
+        print("!"*30)
+        print("WARNING: `vsim` executable not found.")
+        print("The autograder will fail when it attempts to run `vsim` later!")
+        print("!"*30)
+
 
 # ----------------------------------------------------------
 #                           MAIN
@@ -96,6 +106,7 @@ def main():
     # ----------------------------------------------------------
     args = parser.parse_args()
 
+
     lab, project_mpf, tcl_file, tcl_out_file = generate_tcl_mpf_filenames(args.lab)
 
     # Get list of students, either via section number, or a students.txt file.
@@ -108,13 +119,17 @@ def main():
         delete_zip=args.delete_zip,
     )
 
-    # TODO use `students` here instead of `args.student_list` because student_list isn't always used.
+    check_vsim_command()
+
     generate_tcl(
         student_data=students_with_submission,
-        tcl_file=tcl_file,
-        tcl_out_file=tcl_out_file,
-        project_mpf=project_mpf,
-        gui=args.gui,
+        lab_tcl_file=tcl_file,
+        lab_name=lab,
+    )
+
+    run_simulations(
+        students=students_with_submission,
+        gui=args.gui
     )
 
 

modelsim-projects/Lab3/adder_true_testbench.vhd → lab-testbenches/lab3/adder_true_testbench.vhd

@@ -16,9 +16,9 @@ architecture TB of adder_true_testbench is
             WIDTH : positive := 8);
         port (
             x, y : in  std_logic_vector(WIDTH-1 downto 0);
-            cin  : in  std_logic;
+            carry_in  : in  std_logic;
             s    : out std_logic_vector(WIDTH-1 downto 0);
-            cout : out std_logic);
+            carry_out : out std_logic);
     end component;
 
     constant TEST_WIDTH  : positive := 8;
@@ -44,39 +44,39 @@ begin  -- TB
         port map (
             x    => x,
             y    => y,
-            cin  => cin,
+            carry_in  => cin,
             s    => s_rc,
-            cout => cout_rc);
+            carry_out => cout_rc);
 
     U_RIPPLE_CARRY2 : adder
         generic map (
             WIDTH => TEST_WIDTH2)
         port map (
             x    => x2,
             y    => y2,
-            cin  => cin,
+            carry_in  => cin,
             s    => s_rc2,
-            cout => cout_rc2);
+            carry_out => cout_rc2);
 
     U_CARRY_LOOKAHEAD1 : adder
         generic map (
             WIDTH => TEST_WIDTH)
         port map (
             x    => x,
             y    => y,
-            cin  => cin,
+            carry_in  => cin,
             s    => s_cl,
-            cout => cout_cl);
+            carry_out => cout_cl);
 
     U_CARRY_LOOKAHEAD2 : adder
         generic map (
             WIDTH => TEST_WIDTH2)
         port map (
             x    => x2,
             y    => y2,
-            cin  => cin,
+            carry_in  => cin,
             s    => s_cl2,
-            cout => cout_cl2);
+            carry_out => cout_cl2);
 
     U_HIERARCHICAL : adder
         generic map (
@@ -85,9 +85,9 @@ begin  -- TB
         port map (
             x    => x,
             y    => y,
-            cin  => cin,
+            carry_in  => cin,
             s    => s_h,
-            cout => cout_h);
+            carry_out => cout_h);
 
     process
         variable error_rc        : integer;
@@ -252,4 +252,4 @@ configuration adder_true_testbench_config of adder_true_testbench is
         end for;
     end for;
 
-end adder_true_testbench_config;
+end adder_true_testbench_config;