Add alpha support for SVE2.1

[CarolineConcatto]

This patch adds new intrinsics and types for supporting SVE2.1. This patch depends on Pull-Request#217
(#217),
because some intrinsic in this specification are also in Pull-Request#217.

Depends on: #217

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[rsandifo-arm]

Some comments below, but LGTM otherwise. Once the SME2 stuff is in, I think we should consolidate the intrinsics that are common between SME2 and SVE2p1, rather than duplicating them. I agree the current form makes sense until then though.

[rsandifo-arm]

I think we should provide the same addressing modes as for LDNT1 gather:

• svld1q_gather[_u64base]_xx(svbool_t pg, svuint64_t zn) (note svuint64_t rather than svint64_t)
• svld1q_gather[_u64base]_offset_xx(svbool_t pg, svuint64_t zn, int64_t offset)
• svld1q_gather[_u64base]_index_xx(svbool_t pg, svuint64_t zn, int64_t index)
• svld1q_gather_[u64]offset[_xx](svbool_t pg, const xx_t *base, svuint64_t offset)
• svld1q_gather_[u64]index[_xx](svbool_t pg, const xx_t *base, svuint64_t index) for 16-bit, 32-bit and 64-bit xx

[CarolineConcatto]

I imagine we should do the same for the ST1Q scatter quadrword, correct?

[rsandifo-arm]

Yeah, same thing there.

[david-arm]

@CarolineConcatto Is there a reason why the pointers for the structured quad-word stores use uint8_t *, instead of the int8_t * for the svld2q, etc?

[rsandifo-arm]

The type is meant to vary with the suffix, so it's uint8_t * for the [_u8] function shown, and would be int8_t * for the [_s8] version.

[david-arm]

Doh! Of course, silly me. :)

[georges-arm]

There is only an unscaled variant of this instruction, so maybe don't have both offset and index?

[rsandifo-arm]

For the other SVE load and store intrinsics, we tried to provide a consistent interface and set of addressing modes. So the deciding factor wasn't so much whether the call mapped to a single instruction, but whether the underlying instruction could easily emulate the mode. “Single instruction” is a bit of nebulous concept anyway for loads and stores, since a single C address expression might need several operations to compute.

Since scaling is just a shift left, I think it's worth providing both index and offset variants.

[georges-arm]

There is only an unscaled version of this instruction? So maybe don't have both index and offset?

[CarolineConcatto]

s/ svuint8_t svpmov_lane_u8_z(svbool_t pn);/ svuint8_t svpmov_u8_z(svbool_t pn);/

[ThomasBamelis]

With the increased use of x4 vectors in 2.1, would it be the right time to introduce svreinterpret variants for x4 types as well?
With data rearranging, load/storing and element wise bit manipulation changing element size can come in quite handy.

[momchil-velikov]

Why are we dropping the _lane part here?

[CarolineConcatto]

Richard pointed out that the other ext do not have lane in it.

// Variants are also available for:
// _s8, _s16, _u16, _s32, _u32, _s64, _u64
// _bf16, _f16, _f32, _f64
svuint8_t svextq_lane[_u8](svuint8_t zdn, svuint8_t zm, uint64_t imm);
Member
@rsandifo-arm rsandifo-arm 3 weeks ago
I'm not sure these should be lane intrinsics. The instructions are really a form of permutation. (FWIW, the corresponding non-Q intrinsics don't have the _lane suffix.)

[momchil-velikov]

OK.

[Lukacma]

Hello @CarolineConcatto,

You have forgotten DUPQ instruction for sve2p1 . Prototype will look like this :

   // Variants are also available for:
   // _s8, _u16, _s16, _u32, _s32, _u64, _s64
   // _bf16, _f16, _f32, _f64
   svuint8_t svdup_laneq[_u8](svuint8_t zn, uint64_t imm_idx);

This is different to svdupq_lane intrinsic and they have different behaviour

[CarolineConcatto]

I merged SVE2.1 and SME2 intrinsics to 1 section. But I am not sure that is the best.

[rsandifo-arm]

This version seems to add the shared SVE2.1/SME intrinsics back into the SME section (with __arm_streaming attributes). Is that deliberate?

I think we should only document each intrinsic once, as in the previous version. It's just that the relationship between streaming/non-streaming/streaming-compatible and SME/SME2/SVE2/SVE2.1 can't be expressed directly using attributes (and so needs to be specified in words instead).

[CarolineConcatto]

_This version seems to add the shared SVE2.1/SME intrinsics back into the SME section (with _arm_streaming attributes). Is that deliberate?

No, they should not be in the SME section with streaming attribute.
I had to split the patch in two. All the tests in GitHub were failing.
So I created a patch to add all the SVE2.1 intrinsics an another to remove the ones that already exist in SME2.

• ab72e2b (HEAD -> sve2.1) Address review comments
• e9e3450 (origin/sve2.1) Remove from SME2 intriniscs that are common with SVE2.1
• 16f9477 Add alpha support for SVE2.1

[rsandifo-arm]

LGTM apart from the typo below.

[rsandifo-arm]

Suggested change

	For convenience, the intrinsics fo these instructions are listed in the
	For convenience, the intrinsics for these instructions are listed in the

[sallyarmneale]

One very minor comment.