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AArch64 special register designations Change range of o0 to [0, 3] #342

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merged 2 commits into from
Oct 28, 2024
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AArch64 special register designations Change range of o0 to [0, 3] #342

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AArch64 special register designations: Change range of o0 to [0, 3]
v01dXYZ Aug 22, 2024
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Merge branch 'main' into patch-1
vhscampos Oct 28, 2024
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3 changes: 2 additions & 1 deletion main/acle.md
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Original file line number Diff line number Diff line change
Expand Up @@ -419,6 +419,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin
* Unified Function Multi Versioning features memtag and memtag2.
* Unified Function Multi Versioning features aes and pmull.
* Unified Function Multi Versioning features sve2-aes and sve2-pmull128.
* Fixed range of operand `o0` (too small) in AArch64 system register designations.

### References

Expand Down Expand Up @@ -5414,7 +5415,7 @@ When specifying a system register to `__arm_rsr`, `__arm_rsr64`, `__arm_rsr128`,

Where:

* `<o0>` is a decimal integer in the range `[0, 1]`
* `<o0>` is a decimal integer in the range `[0, 3]`
* `<op1>`, `<op2>` are decimal integers in the range `[0, 7]`
* `<CRm>`, `<CRn>` are decimal integers in the range `[0, 15]`

Expand Down