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[FMV] Unify aes with pmull and sve2-aes with sve2-pmull128. #352
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According to the Arm Architecture Reference Manual for A-profile architecture you can't have one feature without having the other: ID_AA64ZFR0_EL1.AES, bits [7:4] > FEAT_SVE_AES implements the functionality identified by the value 0b0001. > FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010. > The permitted values are 0b0000 and 0b0010. (The following was removed from the latest release of the specification, but it appears to be a mistake that was not intended to relax the architecture constraints. The discrepancy has been reported) ID_AA64ISAR0_EL1.AES, bits [7:4] > FEAT_AES implements the functionality identified by the value 0b0001. > FEAT_PMULL implements the functionality identified by the value 0b0010. > From Armv8, the permitted values are 0b0000 and 0b0010. Reviewed in ACLE as ARM-software/acle#352
Those features have been unified here: ARM-software/acle#352
Ping |
IMHO from the user(developer) point of view the 'pmull' feature could be useful outside of |
This looks good to me. I don't think there's any point creating aliases when the corresponding command line flags have existed without any need for aliases for many years. |
This case is similar to feat_sha1 and feat_sha256 (you can't have one without having the other), which we decided to unify: #347. I think we should do the same here. |
Agree, now that we have set the precedent for keeping FMV aligned with the command line options, we should stick with it. If a need arises for specifying pmull without aes then they can be added to both (command line and FMV) later. |
…111673) According to the Arm Architecture Reference Manual for A-profile architecture you can't have one feature without having the other: ID_AA64ZFR0_EL1.AES, bits [7:4] > FEAT_SVE_AES implements the functionality identified by the value 0b0001. > FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010. > The permitted values are 0b0000 and 0b0010. (The following was removed from the latest release of the specification, but it appears to be a mistake that was not intended to relax the architecture constraints. The discrepancy has been reported) ID_AA64ISAR0_EL1.AES, bits [7:4] > FEAT_AES implements the functionality identified by the value 0b0001. > FEAT_PMULL implements the functionality identified by the value 0b0010. > From Armv8, the permitted values are 0b0000 and 0b0010. Approved in ACLE as ARM-software/acle#352
…s. (#170) Those features have been unified here: ARM-software/acle#352
I originally tried splitting these features (see relevant pull reguest llvm/llvm-project#110816), but the following came to my attention: According to https://developer.arm.com/documentation/ddi0487/latest Arm Architecture Reference Manual for A-profile architecture: D23.2.83 ID_AA64ZFR0_EL1, SVE Feature ID Register 0 ID_AA64ZFR0_EL1.AES, bits [7:4] > FEAT_SVE_AES implements the functionality identified by the value 0b0001. > FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010. > The permitted values are 0b0000 and 0b0010. Andrew Carlotti suggests that the same applies for ID_AA64ISAR0_EL1.AES (llvm/llvm-project#110816 (comment)) D19.2.61 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0 ID_AA64ISAR0_EL1.AES, bits [7:4] > FEAT_AES implements the functionality identified by the value 0b0001. > FEAT_PMULL implements the functionality identified by the value 0b0010. > From Armv8, the permitted values are 0b0000 and 0b0010. This was removed from the latest release of the Arm Architecture Reference Manual, but it appears to be a mistake that was not intended to relax the architecture constraints. The discrepancy has been reported.
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…lvm#111673) According to the Arm Architecture Reference Manual for A-profile architecture you can't have one feature without having the other: ID_AA64ZFR0_EL1.AES, bits [7:4] > FEAT_SVE_AES implements the functionality identified by the value 0b0001. > FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010. > The permitted values are 0b0000 and 0b0010. (The following was removed from the latest release of the specification, but it appears to be a mistake that was not intended to relax the architecture constraints. The discrepancy has been reported) ID_AA64ISAR0_EL1.AES, bits [7:4] > FEAT_AES implements the functionality identified by the value 0b0001. > FEAT_PMULL implements the functionality identified by the value 0b0010. > From Armv8, the permitted values are 0b0000 and 0b0010. Approved in ACLE as ARM-software/acle#352
I originally tried splitting these features (see relevant pull request llvm/llvm-project#110816), but the following came to my attention:
According to https://developer.arm.com/documentation/ddi0487/latest Arm Architecture Reference Manual for A-profile architecture:
D23.2.83 ID_AA64ZFR0_EL1, SVE Feature ID Register 0
ID_AA64ZFR0_EL1.AES, bits [7:4]
Andrew Carlotti suggests that the same applies for ID_AA64ISAR0_EL1.AES (llvm/llvm-project#110816 (comment))
D19.2.61 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0
ID_AA64ISAR0_EL1.AES, bits [7:4]
This was removed from the latest release of the Arm Architecture Reference Manual, but it appears to be a mistake that was not intended to relax the architecture constraints. The discrepancy has been reported.
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