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[FMV] Unify aes with pmull and sve2-aes with sve2-pmull128. #352

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merged 1 commit into from
Oct 25, 2024

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labrinea
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@labrinea labrinea commented Oct 3, 2024

I originally tried splitting these features (see relevant pull request llvm/llvm-project#110816), but the following came to my attention:

According to https://developer.arm.com/documentation/ddi0487/latest Arm Architecture Reference Manual for A-profile architecture:

D23.2.83 ID_AA64ZFR0_EL1, SVE Feature ID Register 0

ID_AA64ZFR0_EL1.AES, bits [7:4]

FEAT_SVE_AES implements the functionality identified by the value 0b0001.
FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010.
The permitted values are 0b0000 and 0b0010.

Andrew Carlotti suggests that the same applies for ID_AA64ISAR0_EL1.AES (llvm/llvm-project#110816 (comment))

D19.2.61 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0

ID_AA64ISAR0_EL1.AES, bits [7:4]

FEAT_AES implements the functionality identified by the value 0b0001.
FEAT_PMULL implements the functionality identified by the value 0b0010.
From Armv8, the permitted values are 0b0000 and 0b0010.

This was removed from the latest release of the Arm Architecture Reference Manual, but it appears to be a mistake that was not intended to relax the architecture constraints. The discrepancy has been reported.


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labrinea commented Oct 3, 2024

labrinea added a commit to labrinea/llvm-project that referenced this pull request Oct 9, 2024
According to the Arm Architecture Reference Manual for A-profile
architecture you can't have one feature without having the other:

ID_AA64ZFR0_EL1.AES, bits [7:4]

> FEAT_SVE_AES implements the functionality identified by the value 0b0001.
> FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010.
> The permitted values are 0b0000 and 0b0010.

(The following was removed from the latest release of the specification, but
it appears to be a mistake that was not intended to relax the architecture
constraints. The discrepancy has been reported)

ID_AA64ISAR0_EL1.AES, bits [7:4]

> FEAT_AES implements the functionality identified by the value 0b0001.
> FEAT_PMULL implements the functionality identified by the value 0b0010.
> From Armv8, the permitted values are 0b0000 and 0b0010.

Reviewed in ACLE as ARM-software/acle#352
labrinea added a commit to labrinea/llvm-test-suite that referenced this pull request Oct 9, 2024
@labrinea
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Ping

@DanielKristofKiss
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IMHO from the user(developer) point of view the 'pmull' feature could be useful outside of aes so in cases it could be more expressive to say pmull instead of aes when really only pmull is used actually from the feature set.
(it would be fine if that is just an alias to aes internally)

@andrewcarlotti
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This looks good to me. I don't think there's any point creating aliases when the corresponding command line flags have existed without any need for aliases for many years.

@labrinea
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This case is similar to feat_sha1 and feat_sha256 (you can't have one without having the other), which we decided to unify: #347. I think we should do the same here.

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tmatheson-arm commented Oct 23, 2024

This case is similar to feat_sha1 and feat_sha256 (you can't have one without having the other), which we decided to unify: #347. I think we should do the same here.

Agree, now that we have set the precedent for keeping FMV aligned with the command line options, we should stick with it. If a need arises for specifying pmull without aes then they can be added to both (command line and FMV) later.

labrinea added a commit to llvm/llvm-project that referenced this pull request Oct 23, 2024
…111673)

According to the Arm Architecture Reference Manual for A-profile
architecture you can't have one feature without having the other:

ID_AA64ZFR0_EL1.AES, bits [7:4]

> FEAT_SVE_AES implements the functionality identified by the value
0b0001.
> FEAT_SVE_PMULL128 implements the functionality identified by the value
0b0010.
> The permitted values are 0b0000 and 0b0010.

(The following was removed from the latest release of the specification,
but it appears to be a mistake that was not intended to relax the
architecture constraints. The discrepancy has been reported)

ID_AA64ISAR0_EL1.AES, bits [7:4]

> FEAT_AES implements the functionality identified by the value 0b0001.
> FEAT_PMULL implements the functionality identified by the value
0b0010.
> From Armv8, the permitted values are 0b0000 and 0b0010.

Approved in ACLE as ARM-software/acle#352
labrinea added a commit to llvm/llvm-test-suite that referenced this pull request Oct 23, 2024
I originally tried splitting these features (see relevant pull reguest
llvm/llvm-project#110816), but the following came
to my attention:

According to https://developer.arm.com/documentation/ddi0487/latest
Arm Architecture Reference Manual for A-profile architecture:

D23.2.83 ID_AA64ZFR0_EL1, SVE Feature ID Register 0

ID_AA64ZFR0_EL1.AES, bits [7:4]

> FEAT_SVE_AES implements the functionality identified by the value 0b0001.
> FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010.
> The permitted values are 0b0000 and 0b0010.

Andrew Carlotti suggests that the same applies for ID_AA64ISAR0_EL1.AES
(llvm/llvm-project#110816 (comment))

D19.2.61 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0

ID_AA64ISAR0_EL1.AES, bits [7:4]

> FEAT_AES implements the functionality identified by the value 0b0001.
> FEAT_PMULL implements the functionality identified by the value 0b0010.
> From Armv8, the permitted values are 0b0000 and 0b0010.

This was removed from the latest release of the Arm Architecture Reference Manual,
but it appears to be a mistake that was not intended to relax the architecture
constraints. The discrepancy has been reported.
@vhscampos vhscampos merged commit bd07927 into ARM-software:main Oct 25, 2024
4 checks passed
@labrinea labrinea deleted the fmv-aes-pmull branch October 30, 2024 12:59
NoumanAmir657 pushed a commit to NoumanAmir657/llvm-project that referenced this pull request Nov 4, 2024
…lvm#111673)

According to the Arm Architecture Reference Manual for A-profile
architecture you can't have one feature without having the other:

ID_AA64ZFR0_EL1.AES, bits [7:4]

> FEAT_SVE_AES implements the functionality identified by the value
0b0001.
> FEAT_SVE_PMULL128 implements the functionality identified by the value
0b0010.
> The permitted values are 0b0000 and 0b0010.

(The following was removed from the latest release of the specification,
but it appears to be a mistake that was not intended to relax the
architecture constraints. The discrepancy has been reported)

ID_AA64ISAR0_EL1.AES, bits [7:4]

> FEAT_AES implements the functionality identified by the value 0b0001.
> FEAT_PMULL implements the functionality identified by the value
0b0010.
> From Armv8, the permitted values are 0b0000 and 0b0010.

Approved in ACLE as ARM-software/acle#352
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5 participants