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GCS ACLE #364

Merged
merged 4 commits into from
Jan 15, 2025
Merged

GCS ACLE #364

merged 4 commits into from
Jan 15, 2025

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yury-khrustalev
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@yury-khrustalev yury-khrustalev commented Nov 25, 2024

This is to continue discussion started in #260.


name: Pull request
about: Technical issues, document format problems, bugs in scripts or feature proposal.


@yury-khrustalev yury-khrustalev mentioned this pull request Nov 25, 2024
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The only difference compared to #260 is use of non-const type for GCS pointer (an relevant change in wording).

at compile time if (1) is true which can be feature tested. With (C)
there is no obvious feature test for the presence of the intrinsics.

The future direction is to make intrinsics available unconditionally
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@DanielKristofKiss DanielKristofKiss Nov 25, 2024

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This is how other intrinsics are defined already in practice (gcc, clang at least)
Macro just there to indicate to the user the availability of the intrinsics.

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Thank you for clarification. I've changed the wording, let me know if it's better now.

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+1 from me, just a note from me.
let see what others says.

@yury-khrustalev yury-khrustalev force-pushed the gcs branch 2 times, most recently from 70ac9c6 to a6e18dd Compare December 2, 2024 11:37
Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com>
@john-brawn-arm
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LGTM

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LGTM

@vhscampos vhscampos merged commit 67e0c53 into ARM-software:main Jan 15, 2025
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@@ -1713,6 +1713,15 @@ mechanisms such as function attributes.
Pointer Authentication extension (FEAT_PAuth_LR) are available on the target.
It is undefined otherwise.

### Guarded Control Stack

`__ARM_FEATURE_GCS_DEFAULT` is defined to `1` if the code generation is

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is set to


Checks for hardware features at runtime using the CHKFEAT hint instruction.
`__chkfeat` returns a bitmask where a bit is set if the same bit in the
input argument is set and the corresponding feature is enabled. (Note: for

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Don't embed notes in a paragraph. Put the note after the table.

@@ -4820,6 +4844,60 @@ two pointers, ignoring the tags.
The return value is the sign-extended result of the computation.
The tag bits in the input pointers are ignored for this operation.

# Guarded Control Stack intrinsics

## Introduction

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This heading is unnecessary.

Guarded Control Stack (GCS) extension. The GCS instructions are present
in the AArch64 execution state only.

When GCS protection is enabled then function calls also save the return

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enabled, then


When GCS protection is enabled then function calls also save the return
address to a separate stack, the GCS, that is checked against the actual
return address when the function returns. At runtime GCS protection can

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runtime, GCS


Simplest is (A), but it does not allow asynchronously disabling GCS,
for that at least (B) is needed since the intrinsics must do something
reasonable if GCS is disabled. Asynchronous disable is e.g. needed to

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is, for example, needed


(C) is similar to (B) but allows using the intrinsics even if GCS is
guaranteed to be disabled. The intrinsics are expected to be used
behind runtime check for (3) since they don't do anything useful

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(3) because they do not do

at compile time if (1) is true which can be feature tested. With (C)
there is no obvious feature test for the presence of the intrinsics.

Since intrinsics are available unconditionally and runtime checks

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Because intrinsics

The type of the intrinsics is based on the `void *` GCS pointer
type and `uint64_t` GCS entry type. The GCS pointer could be
`uint64_t *`, but void is more general in that it allows
different access to the GCS (e.g. accessing entries as pointers or

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GCS, for example, accessing entries as pointers or
bytes.

type and `uint64_t` GCS entry type. The GCS pointer could be
`uint64_t *`, but void is more general in that it allows
different access to the GCS (e.g. accessing entries as pointers or
bytes). A GCS entry is usually a code pointer, but the architecture

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A GCS entry is usually a code pointer. However, the architecture
requires it to be 8 bytes, even with ILP32, and it might be a special
token that requires bit operations to detect. Therefore, fixed width
unsigned int type is the most appropriate.

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6 participants