BSA/SBSA register offset #101
Description
This environment is with QEMU based solution where Avery VIPs are connected as PCIe RC and EP. EP is acting as exerciser.
BAR2 contains offset of SBSA register. Host writes the base address as 0x81100000. When it reads back the register it gets a value 0x81100004. This is because lower four bits of the BAR are read only and indicates memory type.
Host while configuring SBSA register should mask lower 4 bits. But it is always treating 0x81100004 as base address of SBSA register.
For e.g. To configure "MSI Control Register" Host should initiate MWR at 0x81100000, but it starts at 0x81100004.
Please confirm if it is intentional or a miss in the code.