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jeromecoutantjeromecoutant
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STM32L476: comments update
1 parent 757944e commit 448f501

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-53
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2 files changed

+49
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‎targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device/system_stm32l4xx.c‎

Lines changed: 25 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -26,21 +26,19 @@
2626
*
2727
* This file configures the system clock as follows:
2828
*=============================================================================
29-
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
30-
* | (external 8 MHz clock) | (internal 16 MHz)
31-
* | 2- PLL_HSE_XTAL | or PLL_MSI
32-
* | (external 8 MHz xtal) | (internal 4 MHz)
33-
*-----------------------------------------------------------------------------
34-
* SYSCLK(MHz) | 48 | 80
35-
*-----------------------------------------------------------------------------
36-
* AHBCLK (MHz) | 48 | 80
37-
*-----------------------------------------------------------------------------
38-
* APB1CLK (MHz) | 48 | 80
39-
*-----------------------------------------------------------------------------
40-
* APB2CLK (MHz) | 48 | 80
41-
*-----------------------------------------------------------------------------
42-
* USB capable (48 MHz precise clock) | YES | NO
43-
*-----------------------------------------------------------------------------
29+
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
30+
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
31+
*---------------------------------------------------------------------------------------------
32+
* SYSCLK(MHz) | 48 | 80 | 80
33+
*---------------------------------------------------------------------------------------------
34+
* AHBCLK (MHz) | 48 | 80 | 80
35+
*---------------------------------------------------------------------------------------------
36+
* APB1CLK (MHz) | 48 | 80 | 80
37+
*---------------------------------------------------------------------------------------------
38+
* APB2CLK (MHz) | 48 | 80 | 80
39+
*---------------------------------------------------------------------------------------------
40+
* USB capable (48 MHz precise clock) | YES | NO | YES
41+
*---------------------------------------------------------------------------------------------
4442
*=============================================================================
4543
******************************************************************************
4644
* @attention
@@ -547,15 +545,15 @@ uint8_t SetSysClock_PLL_MSI(void)
547545
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
548546
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
549547

550-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
551-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
548+
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
549+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
552550
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
553551
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
554-
RCC_OscInitStruct.PLL.PLLM = 6;
555-
RCC_OscInitStruct.PLL.PLLN = 40;
556-
RCC_OscInitStruct.PLL.PLLP = 7;
557-
RCC_OscInitStruct.PLL.PLLQ = 4;
558-
RCC_OscInitStruct.PLL.PLLR = 4;
552+
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
553+
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
554+
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
555+
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
556+
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
559557
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
560558
{
561559
return 0; // FAIL
@@ -564,14 +562,14 @@ uint8_t SetSysClock_PLL_MSI(void)
564562
HAL_RCCEx_EnableMSIPLLMode();
565563
/* Select MSI output as USB clock source */
566564
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
567-
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
565+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
568566
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
569567
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
570568
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
571-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
572-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
573-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
574-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
569+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
570+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
571+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
572+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; /* 40 MHz */
575573
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
576574
{
577575
return 0; // FAIL

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/system_stm32l4xx.c‎

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -26,21 +26,19 @@
2626
*
2727
* This file configures the system clock as follows:
2828
*=============================================================================
29-
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
30-
* | (external 8 MHz clock) | (internal 16 MHz)
31-
* | 2- PLL_HSE_XTAL | or PLL_MSI
32-
* | (external 8 MHz xtal) | (internal 4 MHz)
33-
*-----------------------------------------------------------------------------
34-
* SYSCLK(MHz) | 48 | 80
35-
*-----------------------------------------------------------------------------
36-
* AHBCLK (MHz) | 48 | 80
37-
*-----------------------------------------------------------------------------
38-
* APB1CLK (MHz) | 48 | 80
39-
*-----------------------------------------------------------------------------
40-
* APB2CLK (MHz) | 48 | 80
41-
*-----------------------------------------------------------------------------
42-
* USB capable (48 MHz precise clock) | YES | NO
43-
*-----------------------------------------------------------------------------
29+
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
30+
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
31+
*---------------------------------------------------------------------------------------------
32+
* SYSCLK(MHz) | 48 | 80 | 80
33+
*---------------------------------------------------------------------------------------------
34+
* AHBCLK (MHz) | 48 | 80 | 80
35+
*---------------------------------------------------------------------------------------------
36+
* APB1CLK (MHz) | 48 | 80 | 80
37+
*---------------------------------------------------------------------------------------------
38+
* APB2CLK (MHz) | 48 | 80 | 80
39+
*---------------------------------------------------------------------------------------------
40+
* USB capable (48 MHz precise clock) | YES | NO | YES
41+
*---------------------------------------------------------------------------------------------
4442
*=============================================================================
4543
******************************************************************************
4644
* @attention
@@ -548,14 +546,14 @@ uint8_t SetSysClock_PLL_MSI(void)
548546
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
549547

550548
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
551-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
549+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
552550
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
553551
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
554-
RCC_OscInitStruct.PLL.PLLM = 6;
555-
RCC_OscInitStruct.PLL.PLLN = 40;
556-
RCC_OscInitStruct.PLL.PLLP = 7;
557-
RCC_OscInitStruct.PLL.PLLQ = 4;
558-
RCC_OscInitStruct.PLL.PLLR = 4;
552+
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
553+
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
554+
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
555+
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
556+
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
559557
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
560558
{
561559
return 0; // FAIL
@@ -564,14 +562,14 @@ uint8_t SetSysClock_PLL_MSI(void)
564562
HAL_RCCEx_EnableMSIPLLMode();
565563
/* Select MSI output as USB clock source */
566564
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
567-
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
565+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
568566
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
569567
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
570568
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
571-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
572-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
573-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
574-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
569+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
570+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
571+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
572+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; /* 40 MHz */
575573
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
576574
{
577575
return 0; // FAIL

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