Merge pull request #13939 from jeromecoutant/PR_LSEDRIVE

STM32: LSE DRIVE feature update
ARMmbed · Nov 24, 2020 · ced4aa6 · ced4aa6
2 parents 9de73f8 + 29af76f
commit ced4aa6
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Showing 11 changed files with 30 additions and 39 deletions.
diff --git a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
@@ -38,6 +38,7 @@
 #include "stm32f0xx_ll_tim.h"
 #include "stm32f0xx_ll_pwr.h"
 #include "stm32f0xx_ll_crc.h"
+#include "stm32f0xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/TARGET_STM32F3/objects.h b/targets/TARGET_STM/TARGET_STM32F3/objects.h
@@ -41,6 +41,7 @@
 #include "stm32f3xx_ll_pwr.h"
 #include "stm32f3xx_ll_adc.h"
 #include "stm32f3xx_ll_rtc.h"
+#include "stm32f3xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h
@@ -39,6 +39,7 @@
 #include "stm32f4xx_ll_pwr.h"
 #include "stm32f4xx_ll_adc.h"
 #include "stm32f4xx_ll_rtc.h"
+#include "stm32f4xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/TARGET_STM32F7/objects.h b/targets/TARGET_STM/TARGET_STM32F7/objects.h
@@ -40,6 +40,7 @@
 #include "stm32f7xx_ll_adc.h"
 #include "stm32f7xx_ll_rtc.h"
 #include "stm32f7xx_ll_pwr.h"
+#include "stm32f7xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/TARGET_STM32G4/objects.h b/targets/TARGET_STM/TARGET_STM32G4/objects.h
@@ -24,6 +24,7 @@
 #include "stm32g4xx_ll_tim.h"
 #include "stm32g4xx_ll_pwr.h"
 #include "stm32g4xx_ll_rtc.h"
+#include "stm32g4xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h
@@ -23,9 +23,9 @@
 #include "stm32h7xx_ll_usart.h"
 #include "stm32h7xx_ll_rtc.h"
 #include "stm32h7xx_ll_tim.h"
+#include "stm32h7xx_ll_rcc.h"
 #if defined(DUAL_CORE)
 #include "stm32h7xx_ll_hsem.h"
-#include "stm32h7xx_ll_rcc.h"
 #include "stm32h7xx_ll_cortex.h"
 #endif /* CONFIG_STM32H7_DUAL_CORE */
 #include "stm32h7xx_ll_pwr.h"

diff --git a/targets/TARGET_STM/TARGET_STM32L0/objects.h b/targets/TARGET_STM/TARGET_STM32L0/objects.h
@@ -26,6 +26,7 @@
 #include "stm32l0xx_ll_usart.h"
 #include "stm32l0xx_ll_tim.h"
 #include "stm32l0xx_ll_pwr.h"
+#include "stm32l0xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/TARGET_STM32L4/objects.h b/targets/TARGET_STM/TARGET_STM32L4/objects.h
@@ -29,6 +29,7 @@
 #include "stm32l4xx_ll_tim.h"
 #include "stm32l4xx_ll_rtc.h"
 #include "stm32l4xx_ll_pwr.h"
+#include "stm32l4xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/TARGET_STM32L5/objects.h b/targets/TARGET_STM/TARGET_STM32L5/objects.h
@@ -25,6 +25,7 @@
 #include "stm32l5xx_ll_tim.h"
 #include "stm32l5xx_ll_rtc.h"
 #include "stm32l5xx_ll_pwr.h"
+#include "stm32l5xx_ll_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c
@@ -42,7 +42,7 @@ extern void SetSysClock(void);
 #   if defined(MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL)
 #       define LSE_DRIVE_LOAD_LEVEL    MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
 #   else
-#       if defined(RCC_LSE_HIGHDRIVE_MODE)
+#       if defined(RCC_LSE_HIGHDRIVE_MODE) // STM32F4
 #           define LSE_DRIVE_LOAD_LEVEL    RCC_LSE_LOWPOWER_MODE
 #       else
 #           define LSE_DRIVE_LOAD_LEVEL    RCC_LSEDRIVE_LOW
@@ -70,17 +70,6 @@ extern void SetSysClock(void);
  */
 
 static void LSEDriveConfig(void) {
-    // this config can be changed only when LSE is stopped
-    // LSE could be enabled before a reset and will remain running, disable first
-    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-    {
-        error("LSEDriveConfig : failed to disable LSE\n");
-    }
-
-   // set LSE drive level. Exception only for F4_g2 series
     HAL_PWR_EnableBkUpAccess();
     #if defined(__HAL_RCC_LSEDRIVE_CONFIG)
         __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL);
@@ -180,9 +169,10 @@ void mbed_sdk_init()
     /* Configure the System clock source, PLL Multiplier and Divider factors,
        AHB/APBx prescalers and Flash settings */
 #if defined(LSE_CONFIG_AVAILABLE)
-    // LSE maybe used later, but crystal load drive setting is necessary before 
-    // enabling LSE
-    LSEDriveConfig();
+    // LSE oscillator drive capability set before LSE is started
+    if (!LL_RCC_LSE_IsReady()) {
+        LSEDriveConfig();
+    }
 #endif
     SetSysClock();
     SystemCoreClockUpdate();
@@ -199,16 +189,19 @@ void mbed_sdk_init()
     /* wait until CPU2 wakes up from stop mode */
     while (LL_RCC_D2CK_IsReady() == 0);
 #endif /* CORE_M4 */
+
 #else /* Single core */
     // Update the SystemCoreClock variable.
     SystemCoreClockUpdate();
     HAL_Init();
 
-    /* Configure the System clock source, PLL Multiplier and Divider factors,
-       AHB/APBx prescalers and Flash settings */
 #if defined(LSE_CONFIG_AVAILABLE)
-    LSEDriveConfig();
+    // LSE oscillator drive capability set before LSE is started
+    if (!LL_RCC_LSE_IsReady()) {
+        LSEDriveConfig();
+    }
 #endif
+
     SetSysClock();
     SystemCoreClockUpdate();
 #endif /* DUAL_CORE */

diff --git a/targets/targets.json b/targets/targets.json
@@ -1201,8 +1201,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "macros_add": [
@@ -1415,8 +1414,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "device_has_add": [
@@ -2178,8 +2176,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "overrides": {
@@ -2426,8 +2423,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "extra_labels_add": [
@@ -2534,8 +2530,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "extra_labels_add": [
@@ -2702,8 +2697,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "components_add": [
@@ -2970,8 +2964,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "macros_add": [
@@ -3208,8 +3201,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "macros_add": [
@@ -3745,8 +3737,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "overrides": {
@@ -3851,8 +3842,7 @@
             },
             "lse_drive_load_level": {
                 "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
-                "value": "RCC_LSEDRIVE_LOW",
-                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
+                "value": "RCC_LSEDRIVE_LOW"
             }
         },
         "macros_add": [