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Add test header files and defined behavior for APIs tested using FPGA-Test-Shield #11032
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@mprse, thank you for your changes. |
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hal/analogin_api.h
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@@ -35,9 +35,29 @@ typedef struct analogin_s analogin_t; | |||
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/** | |||
* \defgroup hal_analogin Analogin hal functions | |||
* | |||
* # Defined behaviour | |||
* * The function ::analogin_init initializes the analogin peripheral |
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hal/analogin_api.h
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* # Defined behaviour | ||
* * The function ::analogin_init initializes the analogin peripheral | ||
* * The function ::analogin_read reads the input voltage, represented as a float in the range [0.0, 1.0] | ||
* * The function ::analogin_read_u16 reads the value from analogin pin, represented as an unsigned 16bit value |
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hal/analogout_api.h
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* | ||
* # Defined behaviour | ||
* * The function ::analogout_init initializes the analogin peripheral | ||
* * The function ::analogout_write sets the output voltage, specified as a percentage (float) in range [0.0, 1.0] |
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@@ -70,9 +70,72 @@ extern "C" { | |||
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/** | |||
* \defgroup hal_GeneralI2C I2C Configuration Functions | |||
* |
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* * ::spi_irq_handler_asynch checks for transfer termination conditions, such as buffer overflows or transfer complete | ||
* * ::spi_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise 0 | ||
* * ::spi_abort_asynch aborts an on-going async transfer | ||
* * ::spi_active returns non-zero if the SPI port is active or zero if it is not |
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It may be good to re-use the relevant existing SPI API defined and undefined behavior from the feature branch here:
https://github.com/ARMmbed/mbed-os/blob/feature-hal-spec-spi/hal/spi_api.h#L40-L125
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@mprse This was resolved?
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Yes I created these requirements based on the SPI API defined and undefined behavior from the feature branch.
hal/serial_api.h
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* * The callback given to ::serial_rx_asynch is invoked when the transfer completes | ||
* * ::serial_tx_asynch specifies the logical OR of events to be registered | ||
* * The ::serial_tx_asynch function may use the `DMAUsage` hint to select the appropriate async algorithm | ||
* * ::serial_tx_asynch specifies the character in range 0-254 to be matched |
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Why not 255?
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Looks like 255 is a reserved value:
Line 63 in 7d15882
#define SERIAL_RESERVED_CHAR_MATCH (255) |
hal/serial_api.h
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* * ::serial_tx_abort_asynch flushes the TX hardware buffer if TX FIFO is used | ||
* * ::serial_rx_abort_asynch aborts the ongoing RX transaction | ||
* * ::serial_rx_abort_asynch disables the enabled interupt for RX | ||
* * ::serial_rx_abort_asynch flushes the TX hardware buffer if RX FIFO is used |
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Some of these functions are used from interrupts. It may be good to define and test for maximum function call duration. That would ensure interrupt latency stays low.
hal/serial_api.h
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@@ -108,9 +108,69 @@ extern "C" { | |||
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/** | |||
* \defgroup hal_GeneralSerial Serial Configuration Functions | |||
* | |||
* # Defined behaviour |
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It would also be good to add interrupt latency requirements to defined and/or undefined behavior.
- Correct operation guaranteed when interrupt latency is
< 8 / baudrate_frequency
without flow control - Correct operation guaranteed regardless of interrupt latency with flow control
For reference USB HAL spec has some timing requirements
https://github.com/ARMmbed/mbed-os/blob/master/usb/device/USBPhy/USBPhy.h#L33-L34:
https://github.com/ARMmbed/mbed-os/blob/master/usb/device/USBPhy/USBPhy.h#L58-L61
* Then the operation is successfull. | ||
* | ||
*/ | ||
void fpga_pwm_period_fill_test(PinName pin); |
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void fpga_pwm_period_fill_test(PinName pin); | |
void fpga_pwm_init_free(PinName pin); |
Wrong function name.
@@ -270,7 +270,7 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i | |||
tester.reset(); | |||
} | |||
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void test_init_free(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC) | |||
void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC) |
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void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC) | |
void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts, PinName rts) |
Defaults moved to the header file.
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This comment is still valid. Defaults should always go in the header file.
Conflicts with the base, please rebase. |
I've updated the defined and undefined behavior section of the serial HAL header. The patch is available here: fkjagodzinski@e1c3da6 (I don't have a permission to push to this branch). @mprse, could you cherry-pick fkjagodzinski@e1c3da6 here before you do any rebase/update? Please note, I've left a few |
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PR has been rebased and updated (review comments have been addressed). @c1728p9 @fkjagodzinski Thanks for the review!
@fkjagodzinski Thanks for helping with the requirements for the serial API. I have cherry-picked your changes as you suggested and resolved FIXME notes in the following commit: 9aea87c.
This will be done in the next step. I assume that when this is merged authors of the FPGA tests will review the tests, add missing tests cases for the requirements that can be verified and link the defined behavior to tests. This one is ready for CI/further review. |
Test run: SUCCESSSummary: 11 of 11 test jobs passed |
I think we should establish a naming convention for the test functions. Currently we have a few naming patterns here:
I think we could go with |
I agree that this should be unified, but generally, it is not a problem while the test functions have different names in all test files. This is required to add a mapping to the defined behavior. E.G. in case of spi we had basic test and fpga test and some test functions had the same names. This is why I added |
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Rebased on the master to resolve conflicts. |
@mprse Shall this get our attention now (rebase needed first) ? |
Yes, I will rebase this PR tomorrow. |
Rebased on the master to solve |
CI started |
Please review @maciejbocianski @jamesbeyond . |
Test run: FAILEDSummary: 1 of 4 test jobs failed Failed test jobs:
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Not sure but it looks like some CI issue. Few boards in Jenkins are marked with an exclamation mark with info passed in 0 s, but marked as unstable. |
CI restarted |
Recent updates:
Tested on
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Test run: FAILEDSummary: 3 of 11 test jobs failed Failed test jobs:
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CI aborted , will restart |
Fixed style. |
Test run: SUCCESSSummary: 11 of 11 test jobs passed |
CI passed I think that this one is ready to go in. |
Description
This PR adds header files for FPGA tests with given/when/then description for the test cases and proposition for defined/undefined behavior for the tested APIs.
Please fill free to propose the modification in the defined behavior since this first version has been created mainly based on the description of the functions.
When we agree on the final version of the defined/undefined behavior for the tested APIs, then in the next step we can update the tests (increase coverage) and add a mapping between defined behavior and test cases.
Pull request type
Reviewers
@maciejbocianski @fkjagodzinski @c1728p9 @0xc0170 @jamesbeyond
Notes
BTW I'm OoO from 15/07 to 28/07.