Test: Increase the UART flush delay #12262
Merged
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Summary of changes
SERIAL_FLUSH_TIME_MS
used to wait for the end of the greentea communication in a couple of tests. The original calculation was based on the 16-byte UART Tx FIFO assumption. This is wrong forCY8CPROTO_062_4343W
which uses 128-byte FIFO.This patch is based on the findings from #11909 (comment).
Fixes #11909
Impact of changes
Migration actions required
Documentation
None
Pull request type
Test results
Reviewers
@jamesbeyond, @dustin-crossman