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Fix NRF52840_DK UART driver and adapt FPGA test #12368

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Merged
merged 4 commits into from
Feb 10, 2020
Merged

Fix NRF52840_DK UART driver and adapt FPGA test #12368

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fbe8a8e
NRF52 serial: Trigger TxIrq interrupt manually on enabling
mprse Feb 4, 2020
6a9b4bb
TARGET_NRF52/serial_api.c: Fix style
mprse Feb 4, 2020
22acc79
fpga_ci_test_shield-uart: Disable test cases not supported on NRF5284…
mprse Feb 4, 2020
8fda5a4
Use dedicated macros to skip test cases instead target macro.
mprse Feb 5, 2020
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7 changes: 7 additions & 0 deletions TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -338,7 +338,9 @@ Case cases[] = {
Case("38400, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<38400, 8, ParityNone, 1, false> >),
Case("115200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<115200, 8, ParityNone, 1, false> >),
// stop bits
#if !defined(UART_TWO_STOP_BITS_NOT_SUPPORTED)
Case("9600, 8N2, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, fpga_uart_test_common_no_fc<9600, 8, ParityNone, 2, false> >),
#endif

#if DEVICE_SERIAL_FC
// Every set of pins from every peripheral.
Expand All @@ -355,11 +357,16 @@ Case cases[] = {
Case("115200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<115200, 8, ParityNone, 1, false> >),
// data bits: not tested (some platforms support 8 bits only)
// parity
#if !defined(UART_ODD_PARITY_NOT_SUPPORTED)
Case("9600, 8O1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityOdd, 1, false> >),
#endif
Case("9600, 8E1, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityEven, 1, false> >),
// stop bits
#if !defined(UART_TWO_STOP_BITS_NOT_SUPPORTED)
Case("9600, 8N2, FC on", one_peripheral<UARTPort, DefaultFormFactor, fpga_uart_test_common<9600, 8, ParityNone, 2, false> >),
#endif
#endif

};

utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
Expand Down
42 changes: 25 additions & 17 deletions targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,7 @@
/**
* Missing event typedefs.
*/
typedef enum
{
typedef enum {
NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY),
} nrf_uarte_event_extra_t;

Expand Down Expand Up @@ -505,8 +504,7 @@ static void nordic_nrf5_uart_event_handler_endrx_asynch(int instance)
static void nordic_nrf5_uart_event_handler(int instance)
{
/* DMA buffer is full or has been swapped out by idle timeout. */
if (nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDRX))
{
if (nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDRX)) {
nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDRX);

#if DEVICE_SERIAL_ASYNCH
Expand All @@ -528,16 +526,14 @@ static void nordic_nrf5_uart_event_handler(int instance)
* will setup the wrong DMA buffer and cause data to be lost.
*/
if (nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_RXSTARTED) &&
!nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDRX))
{
!nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDRX)) {
nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_RXSTARTED);

nordic_nrf5_uart_event_handler_rxstarted(instance);
}

/* Tx DMA buffer has been sent. */
if (nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDTX))
{
if (nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDTX)) {
nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDTX);

/* Use SWI to de-prioritize callback. */
Expand Down Expand Up @@ -691,7 +687,7 @@ static void nordic_nrf5_uart_configure_rx(int instance)
{
/* Disable interrupts during confiration. */
nrf_uarte_int_disable(nordic_nrf5_uart_register[instance], NRF_UARTE_INT_RXSTARTED_MASK |
NRF_UARTE_INT_ENDRX_MASK);
NRF_UARTE_INT_ENDRX_MASK);

/* Clear FIFO buffer. */
nrf_atfifo_clear(nordic_nrf5_uart_state[instance].fifo);
Expand Down Expand Up @@ -720,7 +716,7 @@ static void nordic_nrf5_uart_configure_rx(int instance)

/* Enable interrupts again. */
nrf_uarte_int_enable(nordic_nrf5_uart_register[instance], NRF_UARTE_INT_RXSTARTED_MASK |
NRF_UARTE_INT_ENDRX_MASK);
NRF_UARTE_INT_ENDRX_MASK);
}

#if DEVICE_SERIAL_ASYNCH
Expand All @@ -733,7 +729,7 @@ static void nordic_nrf5_uart_configure_rx_asynch(int instance)
{
/* Disable Rx related interrupts. */
nrf_uarte_int_disable(nordic_nrf5_uart_register[instance], NRF_UARTE_INT_RXSTARTED_MASK |
NRF_UARTE_INT_ENDRX_MASK);
NRF_UARTE_INT_ENDRX_MASK);

/* Clear Rx related events. */
nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_RXSTARTED);
Expand Down Expand Up @@ -803,7 +799,7 @@ static void nordic_nrf5_serial_configure(serial_t *obj)
nrf_uarte_task_trigger(nordic_nrf5_uart_register[instance],
NRF_UARTE_TASK_STARTRX);

/* Owner hasn't changed but mode has. Reconfigure. */
/* Owner hasn't changed but mode has. Reconfigure. */
} else if ((uart_object->rx_asynch == true) && (nordic_nrf5_uart_state[instance].rx_asynch == false)) {

nordic_nrf5_uart_configure_rx_asynch(instance);
Expand Down Expand Up @@ -942,8 +938,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
bool done = false;
do {
done = nrf_uarte_event_check(nordic_nrf5_uart_register[instance],
(nrf_uarte_event_t) NRF_UARTE_EVENT_TXDRDY);
} while(done == false);
(nrf_uarte_event_t) NRF_UARTE_EVENT_TXDRDY);
} while (done == false);
}

/* Store pins in serial object. */
Expand Down Expand Up @@ -1008,7 +1004,7 @@ void serial_free(serial_t *obj)
if (nordic_nrf5_uart_state[instance].usage_counter == 0) {

nrf_uarte_disable(nordic_nrf5_uart_register[instance]);

/* Turn NRF_UARTE0_BASE or NRF_UARTE1_BASE power off and on to reset peripheral. */
if (instance == 0) {
*(volatile uint32_t *)0x40002FFC = 0;
Expand All @@ -1022,7 +1018,7 @@ void serial_free(serial_t *obj)
*(volatile uint32_t *)0x40028FFC = 1;
}
#endif

}
}
}
Expand Down Expand Up @@ -1273,6 +1269,8 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
struct serial_s *uart_object = obj;
#endif

int instance = uart_object->instance;

/* Convert Mbed type to Nordic IRQ mask. */
uint32_t type = (irq == TxIrq) ? NORDIC_TX_IRQ : NORDIC_RX_IRQ;

Expand All @@ -1282,10 +1280,20 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
uart_object->mask |= type;
nordic_nrf5_serial_configure(obj);

/* It is required by Mbed HAL API to generate TxIrq interrupt when TXD register is empty (also after enabling TxIrq interrupt).
Driver uses DMA to perform uart transfer and TxIrq is generated after the transfer is finished.
Trigger TxIrq interrupt manually on enabling the TxIrq. */
if (irq == TxIrq) {
if (nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY)) {
nordic_swi_tx_trigger(instance);
}
}
} else {

uart_object->mask &= ~type;
}


}

/** Get character. This is a blocking call, waiting for a character
Expand Down Expand Up @@ -1358,7 +1366,7 @@ void serial_putc(serial_t *obj, int character)
/* Wait until UART is ready to send next character. */
do {
done = nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
} while(done == false);
} while (done == false);

nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);

Expand Down
10 changes: 6 additions & 4 deletions targets/targets.json
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Original file line number Diff line number Diff line change
Expand Up @@ -2441,7 +2441,7 @@
"TRNG",
"FLASH",
"WATCHDOG"
],
],
"release_versions": [
"2",
"5"
Expand All @@ -2464,7 +2464,7 @@
"FSL_RTOS_MBED",
"USE_EXTERNAL_RTC"
],
"default_toolchain": "ARM",
"default_toolchain": "ARM",
"forced_reset_timeout": 7,
"release_versions": [
"2",
Expand Down Expand Up @@ -11097,7 +11097,9 @@
"WSF_MAX_HANDLERS=10",
"MBED_MPU_CUSTOM",
"SWI_DISABLE0",
"NRF52_PAN_20"
"NRF52_PAN_20",
"UART_TWO_STOP_BITS_NOT_SUPPORTED",
"UART_ODD_PARITY_NOT_SUPPORTED"
],
"features": [
"CRYPTOCELL310",
Expand Down Expand Up @@ -14128,7 +14130,7 @@
"smclk_select": "HFXT",
"smclk_div": "DIV2",
"adc_auto_scan": 1
},
},
"release_versions": [
"2",
"5"
Expand Down