Add MAX32670

targets/TARGET_Maxim/CMakeLists.txt

@@ -1,11 +1,12 @@
-# Copyright (c) 2020-2021 ARM Limited. All rights reserved.
+# Copyright (c) 2022 ARM Limited. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
 
 add_subdirectory(TARGET_MAX32620C EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MAX32625 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MAX32630 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MAX32660 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_MAX32670 EXCLUDE_FROM_ALL)
 
 add_library(mbed-maxim INTERFACE)
 

targets/TARGET_Maxim/TARGET_MAX32670/CMakeLists.txt

@@ -0,0 +1,132 @@
+# Copyright (c) 2022 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(TARGET_MAX32670EVKIT EXCLUDE_FROM_ALL)
+
+if(${MBED_TOOLCHAIN} STREQUAL "ARM")
+ set(LINKER_FILE device/TOOLCHAIN_ARM_STD/MAX32670.sct)
+ set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_max32670.S)
+elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+ set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/max32670.ld)
+ set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_max32670.S)
+endif()
+
+add_library(mbed-max32670 INTERFACE)
+mbed_set_linker_script(mbed-max32670 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+set(MXM_PARTNUMBER MAX32670)
+set(MXM_SOURCE_DIR ./Libraries/PeriphDrivers/Source)
+set(MXM_PERIPH_DRIVER_DIR ./Libraries/PeriphDrivers)
+set(MXM_CMSIS_DIR ./Libraries/CMSIS/Device/Maxim)
+
+target_include_directories(mbed-max32670
+ INTERFACE
+ .
+ device
+
+ ${MXM_PERIPH_DRIVER_DIR}/Include/${MXM_PARTNUMBER}
+ ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Include
+
+ ${MXM_SOURCE_DIR}/AES
+ ${MXM_SOURCE_DIR}/CRC
+ ${MXM_SOURCE_DIR}/DMA
+ ${MXM_SOURCE_DIR}/LP
+ ${MXM_SOURCE_DIR}/FLC
+ ${MXM_SOURCE_DIR}/GPIO
+ ${MXM_SOURCE_DIR}/I2C
+ ${MXM_SOURCE_DIR}/I2S 
+ ${MXM_SOURCE_DIR}/ICC
+ ${MXM_SOURCE_DIR}/RTC
+ ${MXM_SOURCE_DIR}/SPI
+ ${MXM_SOURCE_DIR}/SYS
+ ${MXM_SOURCE_DIR}/TMR
+ ${MXM_SOURCE_DIR}/TRNG
+ ${MXM_SOURCE_DIR}/UART
+ ${MXM_SOURCE_DIR}/WDT
+)
+
+target_sources(mbed-max32670
+ INTERFACE
+ PeripheralPins.c
+ gpio_api.c
+ gpio_irq_api.c
+ i2c_api.c
+ pinmap.c
+ port_api.c
+ rtc_api.c
+ serial_api.c
+ sleep.c
+ spi_api.c
+ us_ticker.c
+ lp_ticker.c
+ flash_api.c
+ watchdog_api.c
+
+ ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Source/system_max32670.c
+
+ ${MXM_SOURCE_DIR}/AES/aes_me15.c
+ ${MXM_SOURCE_DIR}/AES/aes_revb.c
+
+ ${MXM_SOURCE_DIR}/CRC/crc_me15.c
+ ${MXM_SOURCE_DIR}/CRC/crc_reva.c
+
+ ${MXM_SOURCE_DIR}/SYS/mxc_assert.c
+ ${MXM_SOURCE_DIR}/SYS/mxc_delay.c
+ ${MXM_SOURCE_DIR}/SYS/mxc_lock.c
+ ${MXM_SOURCE_DIR}/SYS/pins_me15.c
+ ${MXM_SOURCE_DIR}/SYS/sys_me15.c
+
+ ${MXM_SOURCE_DIR}/DMA/dma_me15.c
+ ${MXM_SOURCE_DIR}/DMA/dma_reva.c
+
+ ${MXM_SOURCE_DIR}/LP/lp_me15.c
+
+ ${MXM_SOURCE_DIR}/FLC/flc_common.c
+ ${MXM_SOURCE_DIR}/FLC/flc_me15.c
+ ${MXM_SOURCE_DIR}/FLC/flc_reva.c
+ ${MXM_SOURCE_DIR}/FLC/flc_revb.c
+
+ ${MXM_SOURCE_DIR}/GPIO/gpio_common.c
+ ${MXM_SOURCE_DIR}/GPIO/gpio_me15.c
+ ${MXM_SOURCE_DIR}/GPIO/gpio_reva.c
+
+ ${MXM_SOURCE_DIR}/I2C/i2c_me15.c
+ ${MXM_SOURCE_DIR}/I2C/i2c_reva.c
+
+ ${MXM_SOURCE_DIR}/I2S/i2s_me15.c
+ ${MXM_SOURCE_DIR}/I2S/i2s_reva.c
+
+ ${MXM_SOURCE_DIR}/ICC/icc_common.c
+ ${MXM_SOURCE_DIR}/ICC/icc_me15.c
+ ${MXM_SOURCE_DIR}/ICC/icc_reva.c
+
+ ${MXM_SOURCE_DIR}/RTC/rtc_me15.c
+ ${MXM_SOURCE_DIR}/RTC/rtc_reva.c
+
+ ${MXM_SOURCE_DIR}/SPI/spi_me15.c
+ ${MXM_SOURCE_DIR}/SPI/spi_reva.c
+
+ ${MXM_SOURCE_DIR}/TMR/tmr_common.c
+ ${MXM_SOURCE_DIR}/TMR/tmr_me15.c
+ ${MXM_SOURCE_DIR}/TMR/tmr_revb.c
+
+ ${MXM_SOURCE_DIR}/TRNG/trng_me15.c
+ ${MXM_SOURCE_DIR}/TRNG/trng_revb.c
+
+ ${MXM_SOURCE_DIR}/UART/uart_common.c
+ ${MXM_SOURCE_DIR}/UART/uart_me15.c
+ ${MXM_SOURCE_DIR}/UART/uart_revb.c
+
+ ${MXM_SOURCE_DIR}/WDT/wdt_common.c
+ ${MXM_SOURCE_DIR}/WDT/wdt_me15.c
+ ${MXM_SOURCE_DIR}/WDT/wdt_revb.c
+
+ ${STARTUP_FILE}
+)
+
+target_link_libraries(mbed-max32670
+ INTERFACE 
+ mbed-maxim
+)
+
+

targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h

@@ -0,0 +1,117 @@
+/**
+ * @file aes_key_regs.h
+ * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _AES_KEY_REGS_H_
+#define _AES_KEY_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+ #pragma system_include
+#endif
+
+#if defined (__CC_ARM)
+ #pragma anon_unions
+#endif
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup aes_key
+ * @defgroup aes_key_registers AES_KEY_Registers
+ * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
+ * @details AES Key Registers.
+ */
+
+/**
+ * @ingroup aes_key_registers
+ * Structure type to access the AES_KEY Registers.
+ */
+typedef struct {
+ __IO uint32_t aes_key0; /**< <tt>\b 0x00:</tt> AES_KEY AES_KEY0 Register */
+ __IO uint32_t aes_key1; /**< <tt>\b 0x04:</tt> AES_KEY AES_KEY1 Register */
+ __IO uint32_t aes_key2; /**< <tt>\b 0x08:</tt> AES_KEY AES_KEY2 Register */
+ __IO uint32_t aes_key3; /**< <tt>\b 0x0C:</tt> AES_KEY AES_KEY3 Register */
+ __IO uint32_t aes_key4; /**< <tt>\b 0x10:</tt> AES_KEY AES_KEY4 Register */
+ __IO uint32_t aes_key5; /**< <tt>\b 0x14:</tt> AES_KEY AES_KEY5 Register */
+ __IO uint32_t aes_key6; /**< <tt>\b 0x18:</tt> AES_KEY AES_KEY6 Register */
+ __IO uint32_t aes_key7; /**< <tt>\b 0x1C:</tt> AES_KEY AES_KEY7 Register */
+} mxc_aes_key_regs_t;
+
+/* Register offsets for module AES_KEY */
+/**
+ * @ingroup aes_key_registers
+ * @defgroup AES_KEY_Register_Offsets Register Offsets
+ * @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: <tt> 0x001C</tt> */ 
+/**@} end of group aes_key_registers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AES_KEY_REGS_H_ */