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[LPC15XX] Fix Clock Configuration #1571

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merged 1 commit into from
Feb 29, 2016
Merged

[LPC15XX] Fix Clock Configuration #1571

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6 changes: 3 additions & 3 deletions libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -73,14 +73,14 @@
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.5..7> PSEL: Post Divider Selection
// <o.6..7> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SYSPLLCTRL_Val 0x00000005 // Reset value: 0x000
#define SYSPLLCTRL_Val 0x00000045 // Reset value: 0x000
//
// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
Expand Down Expand Up @@ -156,7 +156,7 @@
// <2=> P = 4
// <3=> P = 8
// </h>
#define SCTPLLCTRL_Val 0x00000005 // Reset value: 0x000
#define SCTPLLCTRL_Val 0x00000045 // Reset value: 0x000
//
// <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
// <0=> IRC Oscillator
Expand Down