Minor update to tools - logging of tests and output

README.md

@@ -95,6 +95,7 @@ Silicon Labs:
 * [EFM32 Leopard Gecko](https://developer.mbed.org/platforms/EFM32-Leopard-Gecko/) (Cortex-M3)
 * [EFM32 Giant Gecko](https://developer.mbed.org/platforms/EFM32-Giant-Gecko/) (Cortex-M3)
 * [EFM32 Wonder Gecko](https://developer.mbed.org/platforms/EFM32-Wonder-Gecko/) (Cortex-M4)
+* [EFM32 Pearl Gecko](https://developer.mbed.org/platforms/EFM32-Pearl-Gecko/) (Cortex-M4)
 
 Atmel:
 * [SAM R21 XPRO](https://developer.mbed.org/platforms/SAMR21-XPRO/) (Cortex-M0+)

hal/common/critical.c

@@ -15,7 +15,7 @@
  * limitations under the License.
  */
 
-
+#define __STDC_LIMIT_MACROS
 #include <stdint.h>
 #include <stddef.h>
 #include "cmsis.h"

hal/common/error.c

@@ -18,6 +18,7 @@
 #include "device.h"
 #include "toolchain.h"
 #include "mbed_error.h"
+#include "mbed_interface.h"
 #if DEVICE_STDIO_MESSAGES
 #include <stdio.h>
 #endif

hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c

@@ -49,8 +49,15 @@ void FPUEnable(void);
 
 #endif
 
+#define FRQCR_IFC_MSK          (0x0030)
+#define FRQCR_IFC_SHFT         (8)
+#define FRQCR_IFC_1P1          (0) /* x1/1 */
+#define FRQCR_IFC_2P3          (1) /* x2/3 */
+#define FRQCR_IFC_1P3          (3) /* x1/3 */
+
 uint32_t IRQNestLevel;
 unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
 
 
 /**
@@ -198,6 +205,35 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq)
     }
 }
 
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock.
+ */
+void SystemCoreClockUpdate (void)
+{
+    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
+
+    switch (frqcr_ifc) {
+        case FRQCR_IFC_1P1:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
+            break;
+        case FRQCR_IFC_2P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
+            break;
+        case FRQCR_IFC_1P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
+            break;
+        default:
+            /* do nothing */
+            break;
+    }
+}
+
+
 /**
  * Initialize the system
  *

hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h

@@ -43,6 +43,8 @@
 extern "C" {
 #endif
 
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
 typedef void(*IRQHandler)();
 uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
 uint32_t InterruptHandlerUnregister(IRQn_Type);

hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c

@@ -49,8 +49,15 @@ void FPUEnable(void);
 
 #endif
 
+#define FRQCR_IFC_MSK          (0x0030)
+#define FRQCR_IFC_SHFT         (8)
+#define FRQCR_IFC_1P1          (0) /* x1/1 */
+#define FRQCR_IFC_2P3          (1) /* x2/3 */
+#define FRQCR_IFC_1P3          (3) /* x1/3 */
+
 uint32_t IRQNestLevel;
 unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
 
 
 /**
@@ -198,6 +205,35 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq)
     }
 }
 
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock.
+ */
+void SystemCoreClockUpdate (void)
+{
+    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
+
+    switch (frqcr_ifc) {
+        case FRQCR_IFC_1P1:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
+            break;
+        case FRQCR_IFC_2P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
+            break;
+        case FRQCR_IFC_1P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
+            break;
+        default:
+            /* do nothing */
+            break;
+    }
+}
+
+
 /**
  * Initialize the system
  *

hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h

@@ -43,6 +43,8 @@
 extern "C" {
 #endif
 
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
 typedef void(*IRQHandler)();
 uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
 uint32_t InterruptHandlerUnregister(IRQn_Type);

tools/build_api.py

@@ -383,8 +383,6 @@ def build_library(src_paths, build_path, target, toolchain_name,
             if toolchain_output:
                 cur_result["output"] += toolchain_output
 
-            cur_result["output"] += str(e)
-
             add_result_to_report(report, cur_result)
 
         # Let Exception propagate

tools/toolchains/__init__.py

@@ -241,8 +241,9 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False,
 
         self.mp_pool = None
 
-        if 'UVISOR_PRESENT=1' in self.macros:
+        if 'UVISOR' in self.target.features and 'UVISOR_SUPPORTED' in self.target.extra_labels:
             self.target.core = re.sub(r"F$", '', self.target.core)
+
         self.flags = deepcopy(self.DEFAULT_FLAGS)
 
     def get_output(self):
@@ -253,9 +254,12 @@ def print_notify(self, event, silent=False):
         """
         msg = None
 
-        if event['type'] in ['info', 'debug']:
+        if not self.VERBOSE and event['type'] == 'tool_error':
             msg = event['message']
-
+
+        elif event['type'] in ['info', 'debug']:
+            msg = event['message']
+
         elif event['type'] == 'cc':
             event['severity'] = event['severity'].title()
             event['file'] = basename(event['file'])
@@ -775,9 +779,6 @@ def link_program(self, r, tmp_path, name):
     def default_cmd(self, command):
         self.debug("Command: %s"% ' '.join(command))
         _stdout, _stderr, _rc = run_cmd(command)
-        # Print all warning / erros from stderr to console output
-        for error_line in _stderr.splitlines():
-            print error_line
 
         self.debug("Return: %s"% _rc)