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[NUCLEO_F302R8] and [NUCLEO_L152RE] updates #221

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Merged
merged 5 commits into from
Mar 20, 2014
Merged

[NUCLEO_F302R8] and [NUCLEO_L152RE] updates #221

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a5cb2f4
[NUCLEO_F302R8] Add uvision4 exporter + correct cortex name
bcostm Mar 20, 2014
ad9f894
[NUCLEO_L152RE] Change system clock to 32MHz + restart PLL after deep…
bcostm Mar 20, 2014
a8236d8
[NUCLEO_L152RE] Add more ANALOG_IN, ANALOG_OUT, PWM, SERIAL and SPI pins
bcostm Mar 20, 2014
daefeed
[NUCLEO_L152RE] Change the check of I2C clock frequency + update stop…
bcostm Mar 20, 2014
9ac335a
[NUCLEO_L152RE] Typo corrections
bcostm Mar 20, 2014
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87 changes: 58 additions & 29 deletions libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
* @file system_stm32l1xx.c
* @author MCD Application Team
* @version V1.2.0
* @date 11-January-2014
* @date 14-March-2014
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32L1xx Ultra
* Low power devices, and is generated by the clock configuration
Expand Down Expand Up @@ -43,29 +43,29 @@
*=============================================================================
* System Clock Configuration
*=============================================================================
* System clock source | HSI
* System Clock source | PLL(HSI)
*-----------------------------------------------------------------------------
* SYSCLK | 16000000 Hz
* SYSCLK | 32000000 Hz
*-----------------------------------------------------------------------------
* HCLK | 16000000 Hz
* HCLK | 32000000 Hz
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* HSE Frequency | 8000000 Hz
* HSE Frequency | Not used
*-----------------------------------------------------------------------------
* PLL DIV | Not Used
* PLL DIV | 2
*-----------------------------------------------------------------------------
* PLL MUL | Not Used
* PLL MUL | 4
*-----------------------------------------------------------------------------
* VDD | 3.3 V
*-----------------------------------------------------------------------------
* Vcore | 1.8 V (Range 1)
*-----------------------------------------------------------------------------
* Flash Latency | 0 WS
* Flash Latency | 1 WS
*-----------------------------------------------------------------------------
* Require 48MHz for USB clock | Disabled
*-----------------------------------------------------------------------------
Expand Down Expand Up @@ -149,7 +149,7 @@
/** @addtogroup STM32L1xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 16000000;
uint32_t SystemCoreClock = 32000000;
__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

Expand All @@ -161,7 +161,7 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
* @{
*/

static void SetSysClock(void);
void SetSysClock(void);

/**
* @}
Expand Down Expand Up @@ -206,6 +206,23 @@ void SystemInit (void)
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif

/* ADDED FOR MBED DEBUG PURPOSE */
/*
// Enable the GPIOA peripheral
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
// Output the system clock on MCO pin (PA.08)
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// Select the clock to output on MCO pin (PA.08)
RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCODiv_1);
//RCC_MCOConfig(RCC_MCOSource_HSI, RCC_MCODiv_1);
*/
}

/**
Expand Down Expand Up @@ -305,7 +322,7 @@ void SystemCoreClockUpdate (void)
* @param None
* @retval None
*/
static void SetSysClock(void)
void SetSysClock(void)
{
__IO uint32_t StartUpCounter = 0, HSIStatus = 0;

Expand All @@ -330,42 +347,54 @@ static void SetSysClock(void)

if (HSIStatus == (uint32_t)0x01)
{
/* Flash 0 wait state */
FLASH->ACR &= ~FLASH_ACR_LATENCY;
/* Enable 64-bit access */
FLASH->ACR |= FLASH_ACR_ACC64;

/* Disable Prefetch Buffer */
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTEN;

/* Disable 64-bit access */
FLASH->ACR &= ~FLASH_ACR_ACC64;
/* Flash 1 wait state (latency) */
FLASH->ACR |= FLASH_ACR_LATENCY;


/* Power enable */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;

/* Select the Voltage Range 1 (1.8 V) */
PWR->CR = PWR_CR_VOS_0;



/* Wait Until the Voltage Regulator is ready */
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
{
}

/* HCLK = SYSCLK /1*/

/* PLL configuration */
/* SYSCLK = (HSI 16 MHz * 4) / 2 = 32 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV2);

/* HCLK = 32 MHz */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK /1*/

/* PCLK2 = 32 MHz */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK /1*/
/* PCLK1 = 32 MHz */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;

/* Select HSI as system clock source */

/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}

/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till HSI is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
}
Expand Down
13 changes: 8 additions & 5 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PeripheralNames.h
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Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,7 @@ extern "C" {
#endif

typedef enum {
ADC_1 = (int)ADC1_BASE,
ADC_2 = (int)ADC_BASE
ADC_1 = (int)ADC1_BASE
} ADCName;

typedef enum {
Expand Down Expand Up @@ -69,9 +68,13 @@ typedef enum {
} I2CName;

typedef enum {
PWM_2 = (int)TIM2_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_4 = (int)TIM4_BASE
PWM_2 = (int)TIM2_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_4 = (int)TIM4_BASE,
PWM_5 = (int)TIM5_BASE,
PWM_9 = (int)TIM9_BASE,
PWM_10 = (int)TIM10_BASE,
PWM_11 = (int)TIM11_BASE
} PWMName;

#ifdef __cplusplus
Expand Down
2 changes: 2 additions & 0 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PinNames.h
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Original file line number Diff line number Diff line change
Expand Up @@ -143,6 +143,8 @@ typedef enum {
LED3 = PA_5,
LED4 = PA_5,
USER_BUTTON = PC_13,
SERIAL_TX = PA_2,
SERIAL_RX = PA_3,
USBTX = PA_2,
USBRX = PA_3,
I2C_SCL = PB_8,
Expand Down
92 changes: 75 additions & 17 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/analogin_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -35,23 +35,36 @@
#include "error.h"

static const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN0
{PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN1
{PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN4
{PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN8
{PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN11
{PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN10
{NC, NC, 0}
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN0
{PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN1
{PA_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN2
{PA_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN3
{PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN4
{PA_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN5
{PA_6, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN6
{PA_7, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN7
{PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN8
{PB_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN9
{PB_12, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN18
{PB_13, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN19
{PB_14, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN20
{PB_15, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN21
{PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN10
{PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN11
{PC_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN12
{PC_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN13
{PC_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN14
{PC_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN15
{NC, NC, 0}
};

int adc_inited = 0;

void analogin_init(analogin_t *obj, PinName pin) {

ADC_TypeDef *adc;
ADC_TypeDef *adc;
ADC_InitTypeDef ADC_InitStructure;

// Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object
// Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);

if (obj->adc == (ADCName)NC) {
Expand Down Expand Up @@ -92,31 +105,76 @@ void analogin_init(analogin_t *obj, PinName pin) {
static inline uint16_t adc_read(analogin_t *obj) {
// Get ADC registers structure address
ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
uint8_t channel = 0;

// Configure ADC channel
switch (obj->pin) {
case PA_0:
ADC_RegularChannelConfig(adc, ADC_Channel_0, 1, ADC_SampleTime_4Cycles);
channel = ADC_Channel_0;
break;
case PA_1:
ADC_RegularChannelConfig(adc, ADC_Channel_1, 1, ADC_SampleTime_4Cycles);
channel = ADC_Channel_1;
break;
case PA_2:
channel = ADC_Channel_2;
break;
case PA_3:
channel = ADC_Channel_3;
break;
case PA_4:
ADC_RegularChannelConfig(adc, ADC_Channel_4, 1, ADC_SampleTime_4Cycles);
channel = ADC_Channel_4;
break;
case PA_5:
channel = ADC_Channel_5;
break;
case PA_6:
channel = ADC_Channel_6;
break;
case PA_7:
channel = ADC_Channel_7;
break;
case PB_0:
ADC_RegularChannelConfig(adc, ADC_Channel_8, 1, ADC_SampleTime_4Cycles);
channel = ADC_Channel_8;
break;
case PC_1:
ADC_RegularChannelConfig(adc, ADC_Channel_11, 1, ADC_SampleTime_4Cycles);
case PB_1:
channel = ADC_Channel_9;
break;
case PB_12:
channel = ADC_Channel_18;
break;
case PB_13:
channel = ADC_Channel_19;
break;
case PB_14:
channel = ADC_Channel_20;
break;
case PB_15:
channel = ADC_Channel_21;
break;
case PC_0:
ADC_RegularChannelConfig(adc, ADC_Channel_10, 1, ADC_SampleTime_4Cycles);
channel = ADC_Channel_10;
break;
case PC_1:
channel = ADC_Channel_11;
break;
case PC_2:
channel = ADC_Channel_12;
break;
case PC_3:
channel = ADC_Channel_13;
break;
case PC_4:
channel = ADC_Channel_14;
break;
case PC_5:
channel = ADC_Channel_15;
break;
default:
return 0;
}

ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_4Cycles);

ADC_SoftwareStartConv(adc); // Start conversion

while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
Expand Down
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