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Merged
merged 12 commits into from
Dec 2, 2016
Merged

[NUC472/M453] Fix CI failed tests #3309

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657d90d
[NUC472/M453] Fix I2C issues
ccli8 Nov 10, 2016
e0f97e5
[NUC472/M453] Support separate enable of GPIO IRQ de-bounce
ccli8 Nov 14, 2016
fe883d4
[M453] Fix CI tests-api-analogin failed
ccli8 Nov 15, 2016
35b2ad5
[NUC472] Fix CI tests-api-analogin failed
ccli8 Nov 18, 2016
bb1617c
[M453] Fix EADC module is initialized multiple times
ccli8 Nov 18, 2016
e1acb06
[NUC472] Rename variable name in analog-in
ccli8 Nov 18, 2016
6c1fca6
[M453] Remove SPI MOSI1 and MISO1 pins from pinmap
ccli8 Nov 18, 2016
f4890f6
[NUC472] Remove SPI MOSI1 and MISO1 pins from pinmap
ccli8 Nov 18, 2016
57a22cd
[NUC472/M453] Fix CI I2C EEPROM failed
ccli8 Nov 21, 2016
d24c71f
[NUC472/M453] Correct return of i2c_byte_write() on NAK
ccli8 Nov 22, 2016
1370533
[M453] Fix button naming error
ccli8 Nov 23, 2016
e1995db
[NUC472/M453] Fix spi_master_transfer failed as bit width is 32
ccli8 Nov 25, 2016
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4 changes: 0 additions & 4 deletions targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
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Original file line number Diff line number Diff line change
Expand Up @@ -297,14 +297,12 @@ const PinMap PinMap_UART_CTS[] = {

const PinMap PinMap_SPI_MOSI[] = {
{PA_5, SPI_1, SYS_GPA_MFPL_PA5MFP_SPI1_MOSI},
{PB_0, SPI_0, SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1},
{PB_5, SPI_0, SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0},
{PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MOSI},
{PC_3, SPI_2, SYS_GPC_MFPL_PC3MFP_SPI2_MOSI},
{PC_10, SPI_2, SYS_GPC_MFPH_PC10MFP_SPI2_MOSI},
{PD_13, SPI_2, SYS_GPD_MFPH_PD13MFP_SPI2_MOSI},
{PE_3, SPI_1, SYS_GPE_MFPL_PE3MFP_SPI1_MOSI},
{PE_9, SPI_0, SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1},
{PE_11, SPI_1, SYS_GPE_MFPH_PE11MFP_SPI1_MOSI},
{PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0},

Expand All @@ -313,7 +311,6 @@ const PinMap PinMap_SPI_MOSI[] = {

const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_MISO},
{PB_1, SPI_0, SYS_GPB_MFPL_PB1MFP_SPI0_MISO1},
{PB_3, SPI_0, SYS_GPB_MFPL_PB3MFP_SPI0_MISO0},
{PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_MISO},
{PB_6, SPI_0, SYS_GPB_MFPL_PB6MFP_SPI0_MISO0},
Expand All @@ -322,7 +319,6 @@ const PinMap PinMap_SPI_MISO[] = {
{PC_11, SPI_2, SYS_GPC_MFPH_PC11MFP_SPI2_MISO},
{PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_MISO},
{PD_14, SPI_2, SYS_GPD_MFPH_PD14MFP_SPI2_MISO},
{PE_8, SPI_0, SYS_GPE_MFPH_PE8MFP_SPI0_MISO1},
{PE_10, SPI_1, SYS_GPE_MFPH_PE10MFP_SPI1_MISO},
{PE_10, SPI_0, SYS_GPE_MFPH_PE10MFP_SPI0_MISO0},

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4 changes: 2 additions & 2 deletions targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h
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Expand Up @@ -101,8 +101,8 @@ typedef enum {
LED_GREEN = LED3,
LED_BLUE = LED1,
// Button naming
SW1 = PA_15,
SW2 = PA_14,
SW2 = PA_15,
SW3 = PA_14,

} PinName;

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5 changes: 2 additions & 3 deletions targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c
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Expand Up @@ -64,9 +64,8 @@ void mbed_sdk_init(void)
CLK_SetCoreClock(72000000);

#if DEVICE_ANALOGIN
// FIXME: Check voltage reference for EADC
/* Vref connect to AVDD */
//SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
/* Vref connect to internal */
SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_072V;
#endif

/* Update System Core Clock */
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96 changes: 21 additions & 75 deletions targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -23,76 +23,25 @@
#include "PeripheralPins.h"
#include "nu_modutil.h"

struct nu_adc_var {
uint32_t en_msk;
};

static struct nu_adc_var adc0_var = {
.en_msk = 0
};
static struct nu_adc_var adc1_var = {
.en_msk = 0
};
static struct nu_adc_var adc2_var = {
.en_msk = 0
};
static struct nu_adc_var adc3_var = {
.en_msk = 0
};
static struct nu_adc_var adc4_var = {
.en_msk = 0
};
static struct nu_adc_var adc5_var = {
.en_msk = 0
};
static struct nu_adc_var adc6_var = {
.en_msk = 0
};
static struct nu_adc_var adc7_var = {
.en_msk = 0
};
static struct nu_adc_var adc8_var = {
.en_msk = 0
};
static struct nu_adc_var adc9_var = {
.en_msk = 0
};
static struct nu_adc_var adc10_var = {
.en_msk = 0
};
static struct nu_adc_var adc11_var = {
.en_msk = 0
};
static struct nu_adc_var adc12_var = {
.en_msk = 0
};
static struct nu_adc_var adc13_var = {
.en_msk = 0
};
static struct nu_adc_var adc14_var = {
.en_msk = 0
};
static struct nu_adc_var adc15_var = {
.en_msk = 0
};
static uint32_t eadc_modinit_mask = 0;

static const struct nu_modinit_s adc_modinit_tab[] = {
{ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc0_var},
{ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc1_var},
{ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc2_var},
{ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc3_var},
{ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc4_var},
{ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc5_var},
{ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc6_var},
{ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc7_var},
{ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc8_var},
{ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc9_var},
{ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc10_var},
{ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc11_var},
{ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc12_var},
{ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc13_var},
{ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc14_var},
{ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc15_var},
{ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
{ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, NULL},
};

void analogin_init(analogin_t *obj, PinName pin)
Expand All @@ -107,7 +56,7 @@ void analogin_init(analogin_t *obj, PinName pin)
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);

// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
if (! ((struct nu_adc_var *) modinit->var)->en_msk) {
if (! eadc_modinit_mask) {
// Reset this module if no channel enabled
SYS_ResetModule(modinit->rsetidx);

Expand All @@ -116,9 +65,6 @@ void analogin_init(analogin_t *obj, PinName pin)
// Enable clock of paired channels
CLK_EnableModuleClock(modinit->clkidx);

// Power on ADC
//ADC_POWER_ON(ADC);

// Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
EADC_SetInternalSampleTime(eadc_base, 6);
Expand All @@ -130,9 +76,9 @@ void analogin_init(analogin_t *obj, PinName pin)
pinmap_pinout(pin, PinMap_ADC);

// Configure the sample module Nmod for analog input channel Nch and software trigger source
EADC_ConfigSampleModule(EADC, chn, EADC_SOFTWARE_TRIGGER, chn);
EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn);

((struct nu_adc_var *) modinit->var)->en_msk |= 1 << chn;
eadc_modinit_mask |= 1 << chn;
}

uint16_t analogin_read_u16(analogin_t *obj)
Expand All @@ -141,7 +87,7 @@ uint16_t analogin_read_u16(analogin_t *obj)
uint32_t chn = NU_MODSUBINDEX(obj->adc);

EADC_START_CONV(eadc_base, 1 << chn);
while (EADC_GET_PENDING_CONV(eadc_base) & (1 << chn));
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != (1 << chn));
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
// Just 12 bits are effective. Convert to 16 bits.
// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
Expand Down
58 changes: 41 additions & 17 deletions targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c
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Expand Up @@ -52,22 +52,23 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {

#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))

#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
#define M451_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
#else
#define M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
#endif

#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
#else
#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
#endif
static PinName gpio_irq_debounce_arr[] = {
MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
};

#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
#endif

#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
#else
#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
#ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
#define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
#endif

int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
Expand All @@ -89,13 +90,36 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
//gpio_set(pin);

#if M451_GPIO_IRQ_DEBOUNCE_ENABLE
// Configure de-bounce clock source and sampling cycle time
GPIO_SET_DEBOUNCE_TIME(M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
{
#if MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
// Suppress compiler warning
(void) gpio_irq_debounce_arr;

// Configure de-bounce clock source and sampling cycle time
GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
#else
GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
// Enable de-bounce if the pin is in the de-bounce enable list

// De-bounce defaults to disabled.
GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);

PinName *debounce_pos = gpio_irq_debounce_arr;
PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);

if (pin_index == pin_index_debunce &&
port_index == port_index_debounce) {
// Configure de-bounce clock source and sampling cycle time
GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
break;
}
}
#endif
}

struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;

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