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STM32 NUCLEO-L152RE Update system core clock to 32MHz #3377

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Merged
merged 1 commit into from
Dec 9, 2016
Merged

STM32 NUCLEO-L152RE Update system core clock to 32MHz #3377

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20 changes: 10 additions & 10 deletions targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/system_stm32l1xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,13 +27,13 @@
* | 2- PLL_HSE_XTAL |
* | (external 8 MHz xtal) |
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 24 | 32
* SYSCLK(MHz) | 32 | 32
*-----------------------------------------------------------------------------
* AHBCLK (MHz) | 24 | 32
* AHBCLK (MHz) | 32 | 32
*-----------------------------------------------------------------------------
* APB1CLK (MHz) | 24 | 32
* APB1CLK (MHz) | 32 | 32
*-----------------------------------------------------------------------------
* APB2CLK (MHz) | 24 | 32
* APB2CLK (MHz) | 32 | 32
*-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | NO
*-----------------------------------------------------------------------------
Expand Down Expand Up @@ -540,19 +540,19 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// USBCLK = 48 MHz (8 MHz * 6) --> USB OK
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
}

/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
Expand Down
2 changes: 1 addition & 1 deletion targets/TARGET_STM/mbed_rtx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -584,7 +584,7 @@
#define OS_MAINSTKSIZE 256
#endif
#ifndef OS_CLOCK
#define OS_CLOCK 24000000
#define OS_CLOCK 32000000
#endif

#elif defined(TARGET_NZ32_SC151)
Expand Down