Interrupt stack size unification + test

TESTS/mbed_hal/stack_size_unification/main.cpp

@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2019-2019 ARM Limited
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+
+#ifdef TARGET_RENESAS
+#error [NOT_SUPPORTED] Cortex-A target not supported for this test
+#endif
+
+using namespace utest::v1;
+
+extern osThreadAttr_t _main_thread_attr;
+extern uint32_t mbed_stack_isr_size;
+
+/* Exception for Nordic boards - BLE requires 2KB ISR stack. */
+#if defined(TARGET_NRF5x)
+#define EXPECTED_ISR_STACK_SIZE                  (2048)
+#else
+#define EXPECTED_ISR_STACK_SIZE                  (1024)
+#endif
+
+#if defined(TARGET_NUCLEO_F070RB) || defined(TARGET_NANO100) || defined(TARGET_STM32F072RB) || defined(TARGET_TMPM46B) || defined(TARGET_TMPM066)
+#define EXPECTED_MAIN_THREAD_STACK_SIZE          (3072)
+#else
+#define EXPECTED_MAIN_THREAD_STACK_SIZE          (4096)
+#endif
+
+#define EXPECTED_USER_THREAD_DEFAULT_STACK_SIZE  (4096)
+
+/* Test sizes of ISR stack, main thread stack, default user thread stack.
+ *
+ * On some platforms with lower RAM size (e.g. NUCLEO_F070RB - 16 KB RAM) it is impossible
+ * to create thread with default stack size to check its size, that is why we will
+ * check only macro which specifies default user thread stack.
+ *
+ */
+void stack_size_unification_test()
+{
+    TEST_ASSERT_EQUAL(EXPECTED_ISR_STACK_SIZE, mbed_stack_isr_size);
+    TEST_ASSERT_EQUAL(EXPECTED_MAIN_THREAD_STACK_SIZE, _main_thread_attr.stack_size);
+    TEST_ASSERT_EQUAL(EXPECTED_USER_THREAD_DEFAULT_STACK_SIZE, OS_STACK_SIZE);
+}
+
+utest::v1::status_t test_setup(const size_t number_of_cases)
+{
+    GREENTEA_SETUP(10, "default_auto");
+    return verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+    Case("Stack size unification test", stack_size_unification_test)
+};
+
+Specification specification(test_setup, cases);
+
+int main()
+{
+    return !Harness::run(specification);
+}

TESTS/mbed_hal/stack_size_unification/stack_size_unification.h

@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2019-2019 ARM Limited
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/** \addtogroup hal_rtc_tests
+ *  @{
+ */
+
+#ifndef MBED_STACK_SIZE_UNIFICATION_H
+#define MBED_STACK_SIZE_UNIFICATION_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Test sizes of ISR stack, main thread stack, default user thread stack.
+ *
+ *  Given is Mbed OS configuration.
+ *  When ISR stack, main thread stack, default user thread stack sizes are defined.
+ *  Then ISR stack size is equal to 1 KB,
+ *       main thread stack size is equal to 4 KB,
+ *       default user thread stack size is equal to 4 KB.
+ *
+ * NOTE:
+ * It is impossible to verify RTOS-less thread stack size since all tests are build with RTOS.
+ */
+void stack_size_unification_test(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/

rtos/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c

@@ -25,6 +25,10 @@ extern uint32_t __initial_sp[];
 extern uint32_t __heap_base[];
 extern uint32_t __heap_limit[];
 
+#if !defined(ISR_STACK_SIZE)
+#define ISR_STACK_SIZE ((uint32_t)1024)
+#endif
+
 /*
  * mbed entry point for the MICROLIB toolchain
  *

rtos/TARGET_CORTEX/TOOLCHAIN_ARM_STD/mbed_boot_arm_std.c

@@ -27,11 +27,20 @@
 __value_in_regs struct __argc_argv __rt_lib_init(unsigned heapbase, unsigned heaptop);
 void _platform_post_stackheap_init(void);
 
+#if !defined(ISR_STACK_SIZE)
+#if (defined(__CC_ARM))
+extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Base[];
+extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Length[];
+#define ISR_STACK_START       ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base)
+#define ISR_STACK_SIZE        ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length)
+#endif
+#endif
+
 #if !defined(HEAP_START)
 /* Defined by linker script */
 extern uint32_t Image$$RW_IRAM1$$ZI$$Limit[];
 #define HEAP_START      ((unsigned char*)Image$$RW_IRAM1$$ZI$$Limit)
-#define HEAP_SIZE       ((uint32_t)((uint32_t)INITIAL_SP - (uint32_t)HEAP_START))
+#define HEAP_SIZE       ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START))
 #endif
 
 /*

rtos/TARGET_CORTEX/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c

@@ -29,11 +29,20 @@ static osMutexId_t               env_mutex_id;
 static mbed_rtos_storage_mutex_t env_mutex_obj;
 static osMutexAttr_t             env_mutex_attr;
 
+#if !defined(ISR_STACK_SIZE)
+#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION))
+extern uint32_t               __StackLimit;
+extern uint32_t               __StackTop;
+#define ISR_STACK_START       ((unsigned char*)&__StackLimit)
+#define ISR_STACK_SIZE        ((uint32_t)((uint32_t)&__StackTop - (uint32_t)&__StackLimit))
+#endif
+#endif
+
 #if !defined(HEAP_START)
 /* Defined by linker script */
 extern uint32_t __end__[];
 #define HEAP_START      ((unsigned char*)__end__)
-#define HEAP_SIZE       ((uint32_t)((uint32_t)INITIAL_SP - (uint32_t)HEAP_START))
+#define HEAP_SIZE       ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START))
 #endif
 
 extern void __libc_init_array(void);

rtos/TARGET_CORTEX/mbed_boot.h

@@ -50,11 +50,6 @@ extern "C" {
  * @{
  */
 
-/* Define stack sizes if they haven't been set already */
-#if !defined(ISR_STACK_SIZE)
-#define ISR_STACK_SIZE ((uint32_t)1024)
-#endif
-
 /* Heap limits - only used if set */
 extern unsigned char *mbed_heap_start;
 extern uint32_t mbed_heap_size;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld

@@ -31,6 +31,10 @@
 #include "../memory_zones.h"
 #include "../cmsis_nvic.h"
 
+#if !defined(MBED_BOOT_STACK_SIZE)
+    #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
 MEMORY
 {
   VECTORS (rx)          : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
@@ -66,7 +70,7 @@ MEMORY
  */
 ENTRY(Reset_Handler)
 
-STACK_SIZE = 0x400;
+STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
 /* Size of the vector table in SRAM */
 M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf

@@ -48,8 +48,11 @@ define symbol __ICFEDIT_region_RAM_end__      = ZBT_SRAM2_START + ZBT_SRAM2_SIZE
 
 /*-Sizes-*/
 /* Heap and Stack size */
+if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
+    define symbol MBED_BOOT_STACK_SIZE = 0x400;
+}
 define symbol __ICFEDIT_size_heap__   = 0x200000;
-define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
 /**** End of ICF editor section. ###ICF###*/
 
 define memory mem with size = 4G;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -37,10 +37,14 @@
 #include "../memory_zones.h"
 #include "../cmsis_nvic.h"
 
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
 #if (defined(__stack_size__))
     #define STACK_SIZE  __stack_size__
 #else  
-    #define STACK_SIZE  0x0400
+    #define STACK_SIZE  MBED_BOOT_STACK_SIZE
 #endif
 
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
@@ -56,7 +60,7 @@ LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
    .ANY (+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE)  {  ; RW data
+  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
    .ANY (+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld

@@ -66,7 +66,11 @@ MEMORY
  */
 ENTRY(Reset_Handler)
 
-STACK_SIZE = 0x400;
+#if !defined(MBED_BOOT_STACK_SIZE)
+    #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
 /* Size of the vector table in SRAM */
 M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf

@@ -48,8 +48,11 @@ define symbol __ICFEDIT_region_RAM_end__      = ZBT_SRAM2_START + ZBT_SRAM2_SIZE
 
 /*-Sizes-*/
 /* Heap and Stack size */
+if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
+    define symbol MBED_BOOT_STACK_SIZE = 0x400;
+}
 define symbol __ICFEDIT_size_heap__   = 0x200000;
-define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
 /**** End of ICF editor section. ###ICF###*/
 
 define memory mem with size = 4G;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -37,10 +37,14 @@
 #include "../memory_zones.h"
 #include "../cmsis_nvic.h"
 
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
 #if (defined(__stack_size__))
     #define STACK_SIZE  __stack_size__
 #else  
-    #define STACK_SIZE  0x0400
+    #define STACK_SIZE  MBED_BOOT_STACK_SIZE
 #endif
 
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
@@ -56,7 +60,7 @@ LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
    .ANY (+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE)  {  ; RW data
+  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
    .ANY (+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld

@@ -66,7 +66,11 @@ MEMORY
  */
 ENTRY(Reset_Handler)
 
-STACK_SIZE = 0x400;
+#if !defined(MBED_BOOT_STACK_SIZE)
+    #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
 /* Size of the vector table in SRAM */
 M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf

@@ -48,8 +48,11 @@ define symbol __ICFEDIT_region_RAM_end__      = ZBT_SRAM2_START + ZBT_SRAM2_SIZE
 
 /*-Sizes-*/
 /* Heap and Stack size */
+if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
+    define symbol MBED_BOOT_STACK_SIZE = 0x400;
+}
 define symbol __ICFEDIT_size_heap__   = 0x200000;
-define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
 /**** End of ICF editor section. ###ICF###*/
 
 define memory mem with size = 4G;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct

@@ -37,10 +37,14 @@
 #include "../memory_zones.h"
 #include "../cmsis_nvic.h"
 
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
 #if (defined(__stack_size__))
     #define STACK_SIZE  __stack_size__
 #else  
-    #define STACK_SIZE  0x0400
+    #define STACK_SIZE  MBED_BOOT_STACK_SIZE
 #endif
 
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
@@ -56,7 +60,7 @@ LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
    .ANY (+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE)  {  ; RW data
+  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
    .ANY (+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld

@@ -31,6 +31,10 @@
 #include "../memory_zones.h"
 #include "../cmsis_nvic.h"
 
+#if !defined(MBED_BOOT_STACK_SIZE)
+    #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
 MEMORY
 {
   VECTORS (rx)          : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE
@@ -66,7 +70,7 @@ MEMORY
  */
 ENTRY(Reset_Handler)
 
-STACK_SIZE = 0x400;
+STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
 /* Size of the vector table in SRAM */
 M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf

@@ -48,8 +48,11 @@ define symbol __ICFEDIT_region_RAM_end__      = ZBT_SRAM2_START + ZBT_SRAM2_SIZE
 
 /*-Sizes-*/
 /* Heap and Stack size */
+if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
+    define symbol MBED_BOOT_STACK_SIZE = 0x400;
+}
 define symbol __ICFEDIT_size_heap__   = 0x200000;
-define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
 /**** End of ICF editor section. ###ICF###*/
 
 define memory mem with size = 4G;