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DISCO L475VG IOT01A: heap in SRAM2 region #9588

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Feb 4, 2019
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
"name": "bootloader_DISCO_L475VG_IOT01A",
"target_overrides": {
"*": {
"target.app_offset": "0x9800",
"target.header_offset": "0x9000",
"target.app_offset": "0x10400",
"target.header_offset": "0x10000",
"target.bootloader_img": "mbed-bootloader-internal_dfb7cc.bin"
}
}
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -60,11 +60,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
}
RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size { ; RW data 96k L4-SRAM1
.ANY (+RW +ZI)
.ANY (+RW, +Last)
}
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby
.ANY (+RW +ZI)
RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; ZI data 32k L4-ECC-SRAM2
.ANY (+ZI)
}
ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
}
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Original file line number Diff line number Diff line change
Expand Up @@ -152,7 +152,7 @@ SECTIONS
. = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
} > SRAM2

.heap (COPY):
{
Expand Down Expand Up @@ -183,5 +183,6 @@ SECTIONS
PROVIDE(__stack = __StackTop);
/* Check if stack exceeds RAM2 limit */
ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow")

/* Check if bss exceeds __StackLimit */
ASSERT(__bss_end__ <= __StackLimit, "BSS is too big for RAM2")
}
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
}

define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __size_heap__ = 0x10000;
define symbol __size_heap__ = 0x17000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };

Expand All @@ -44,4 +44,4 @@ place at address mem:__intvec_start__ { readonly section .intvec };

place in ROM_region { readonly };
place in SRAM1_region { readwrite, block HEAP };
place in SRAM2_region { block CSTACK };
place in SRAM2_region { first block CSTACK, zeroinit };