Update Toolchain Arm Micro scatter files

platform/mbed_retarget.cpp

@@ -908,13 +908,14 @@ extern "C" long PREFIX(_flen)(FILEHANDLE fh)
 // Do not compile this code for TFM secure target
 #if !defined(COMPONENT_SPE) || !defined(TARGET_TFM)
 
+#if !defined(__MICROLIB)
 #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
 __asm(".global __use_two_region_memory\n\t");
 __asm(".global __use_no_semihosting\n\t");
-
 #else
 #pragma import(__use_two_region_memory)
 #endif
+#endif
 
 #if !defined(HEAP_START)
 // Heap here is considered starting after ZI ends to Stack start
@@ -939,12 +940,14 @@ extern "C" MBED_WEAK __value_in_regs struct __initial_stackheap _mbed_user_setup
     return r;
 }
 
+#if !defined(__MICROLIB)
 extern "C" __value_in_regs struct __argc_argv $Super$$__rt_lib_init(unsigned heapbase, unsigned heaptop);
 
 extern "C" __value_in_regs struct __argc_argv $Sub$$__rt_lib_init(unsigned heapbase, unsigned heaptop)
 {
     return $Super$$__rt_lib_init((unsigned)HEAP_START, (unsigned)HEAP_LIMIT);
 }
+#endif
 
 extern "C" __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
 {

rtos/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c

@@ -16,18 +16,16 @@
  */
 #include <stdlib.h>
 #include <string.h>
+#include <stdint.h>
 
 #include "mbed_boot.h"
 #include "mbed_assert.h"
 
-/* Symbols that are typically defined in startup_<mcu>.S */
-extern uint32_t __initial_sp[];
-extern uint32_t __heap_base[];
-extern uint32_t __heap_limit[];
+extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Base[];
+extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Length[];
 
-#if !defined(ISR_STACK_SIZE)
-#define ISR_STACK_SIZE ((uint32_t)1024)
-#endif
+extern uint32_t               Image$$ARM_LIB_HEAP$$ZI$$Base[];
+extern uint32_t               Image$$ARM_LIB_HEAP$$ZI$$Length[];
 
 /*
  * mbed entry point for the MICROLIB toolchain
@@ -41,12 +39,11 @@ void _main_init(void) __attribute__((section(".ARM.Collect$$$$000000FF")));
 void _main_init(void)
 {
     /* microlib only supports the two region memory model */
+    mbed_stack_isr_start = (unsigned char *) Image$$ARM_LIB_STACK$$ZI$$Base;
+    mbed_stack_isr_size = (uint32_t) Image$$ARM_LIB_STACK$$ZI$$Length;
 
-    mbed_heap_start = (unsigned char *)__heap_base;
-    mbed_heap_size = (uint32_t)__heap_base - (uint32_t)__heap_limit;
-
-    mbed_stack_isr_start = (unsigned char *)((uint32_t)__initial_sp - ISR_STACK_SIZE);
-    mbed_stack_isr_size = ISR_STACK_SIZE;
+    mbed_heap_start = (unsigned char *) Image$$ARM_LIB_HEAP$$ZI$$Base;
+    mbed_heap_size = (uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length;
 
     mbed_init();
     mbed_rtos_start();

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct

@@ -1,19 +1,50 @@
+#! armcc -E
+
 ;SAMD21G18A
-;256KB FLASH (0x40000) @ 0x000000000
-;2KB RAM (0x8000) @ 0x20000000
+; 256KB FLASH (0x40000) @ 0x000000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
+
+; SAMD21G18A: 256KB FLASH (0x40000)
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE             0x40000
+#endif
+
+; 32KB RAM (0x8000) @ 0x20000000
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START            0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE             0x8000
+#endif
+
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+#define VECTOR_SIZE                 0xB8
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
 
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
 
-;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
-LR_IROM1 0x00000000 0x40000  {    ; load region size_region
-    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
-        *.o (RESET, +First)
-        *(InRoot$$Sections)
-        .ANY (+RO)
-    }
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
 
-    ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
-    RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)  {  ; RW data
-        .ANY (+RW +ZI)
-    }
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
 
-}
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
+}

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct

@@ -1,19 +1,50 @@
+#! armcc -E
+
 ;SAMD21J18A
-;256KB FLASH (0x40000) @ 0x000000000
-;2KB RAM (0x8000) @ 0x20000000
+; 256KB FLASH (0x40000) @ 0x000000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
+
+; SAMD21J18A: 256KB FLASH (0x40000)
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE             0x40000
+#endif
+
+; 32KB RAM (0x8000) @ 0x20000000
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START            0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE             0x8000
+#endif
+
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+#define VECTOR_SIZE                 0xB8
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
 
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
 
-;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
-LR_IROM1 0x00000000 0x40000  {    ; load region size_region
-    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
-        *.o (RESET, +First)
-        *(InRoot$$Sections)
-        .ANY (+RO)
-    }
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
 
-    ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
-    RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)  {  ; RW data
-        .ANY (+RW +ZI)
-    }
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
 
-}
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
+}

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct

@@ -1,29 +1,50 @@
-;
-SAML21J18A
-;
-256KB FLASH (0x40000) @ 0x000000000
-;
-2KB RAM (0x8000) @ 0x20000000
-
-
-;
-SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
-LR_IROM1 0x00000000 0x40000  {    ;
-    load region size_region
-    ER_IROM1 0x00000000 0x40000  {  ;
-                                    load address = execution address
-                                            *.o (RESET, +First)
-                                            *(InRoot$$Sections)
-                                            .ANY (+RO)
-                                 }
-
-    ;
-    [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
-            RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)
-    {
-        ;
-        RW data
-        .ANY (+RW +ZI)
-    }
-
-}
+#! armcc -E
+
+;SAMD21J18A
+; 256KB FLASH (0x40000) @ 0x000000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
+
+; SAMD21J18A: 256KB FLASH (0x40000)
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE             0x40000
+#endif
+
+; 32KB RAM (0x8000) @ 0x20000000
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START            0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE             0x8000
+#endif
+
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+#define VECTOR_SIZE                 0xB8
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
+
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
+
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
+}

targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct

@@ -1,19 +1,50 @@
+#! armcc -E
+
 ;SAMR21G18A
-;256KB FLASH (0x40000) @ 0x000000000
-;2KB RAM (0x8000) @ 0x20000000
+; 256KB FLASH (0x40000) @ 0x000000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START            0x00000000
+#endif
+
+; SAMR21G18A: 256KB FLASH (0x40000)
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE             0x40000
+#endif
+
+; 32KB RAM (0x8000) @ 0x20000000
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START            0x20000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE             0x8000
+#endif
+
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE      0x400
+#endif
+
+; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
+#define VECTOR_SIZE                 0xB0
+
+#define RAM_FIXED_SIZE              (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
+
+LR_IROM1  MBED_APP_START  MBED_APP_SIZE  {    ; load region size_region
 
+  ER_IROM1  MBED_APP_START  MBED_APP_SIZE  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
 
-;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
-LR_IROM1 0x00000000 0x40000  {    ; load region size_region
-    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
-        *.o (RESET, +First)
-        *(InRoot$$Sections)
-        .ANY (+RO)
-    }
+  RW_IRAM1  (MBED_RAM_START+VECTOR_SIZE)  (MBED_RAM_SIZE-VECTOR_SIZE)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
 
-    ; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
-    RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0)  {  ; RW data
-        .ANY (+RW +ZI)
-    }
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16))  {
+  }
 
-}
+  ARM_LIB_STACK  (MBED_RAM_START+MBED_RAM_SIZE)  EMPTY  -MBED_BOOT_STACK_SIZE { ; stack
+  }
+}