Pinned Loading

1. RISCV_5_Stage_Pipelined_CPU RISCV_5_Stage_Pipelined_CPU Public

   This is RISCV 5-stage pipelined CPU core implementation in System Verilog. It has Fetch, Decode, Execute, Memory and write back pipelined stages. It also contains a hazard unit which handles the da…

   SystemVerilog

2. RTL-Design-and-Synthesis-Workshop-using-Skywater-130-PDK RTL-Design-and-Synthesis-Workshop-using-Skywater-130-PDK Public

3. Sign-off-Timing-Analysis---Basics-to-advanced-workshop Sign-off-Timing-Analysis---Basics-to-advanced-workshop Public

4. Single_Cycle_RISCV_CPU Single_Cycle_RISCV_CPU Public

   This is single cycle RSICV CPU which implements 30 instructions in RV32I

   SystemVerilog

5. SystemVerilog_Verification_Projects SystemVerilog_Verification_Projects Public

   SystemVerilog

6. UVM_Based_Verification_Projects UVM_Based_Verification_Projects Public

   This repository contains verification projects using UVM based environment. I have implemented these projects during my UVM base verification learning journey.

   SystemVerilog