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Merge pull request #14 from Aharoni-Lab/wireless_fpga
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feat: add support for wireless fpga-based manchester daq
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MarcelMB authored Apr 9, 2024
2 parents 88d9e7c + d8b49f9 commit 7a7e8c5
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3 changes: 1 addition & 2 deletions .gitignore
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*$py.class

# C extensions
*.so
# *.so

# Distribution / packaging
.Python
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downloads/
eggs/
.eggs/
lib/
lib64/
parts/
sdist/
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10 changes: 10 additions & 0 deletions README.md
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Functionality not guaranteed
-<3 jonny)



## Licensing

This package includes software sublicensed from more
restrictive licenses. Those licenses can be found
in the `LICENSE` files in the respective directories
containing the unmodified source material

* `miniscope_io/vendor/opalkelly`
11 changes: 11 additions & 0 deletions docs/api/devices.md
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# Devices

Interfaces to external devices like miniscopes and DAQs

## OpalKelly

```{eval-rst}
.. autoclass:: miniscope_io.devices.opalkelly.okDev
:members:
:undoc-members:
```
3 changes: 3 additions & 0 deletions docs/api/index.md
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:caption: API
data
devices
formats
io
sdcard
exceptions
plots/index
utils
uart_daq
vendor/index
```
11 changes: 11 additions & 0 deletions docs/api/uart_daq.md
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# UART Daq

(Some description of what this module does, can happen either here in markdown
or in the module docstring as RST)

```{eval-rst}
.. automodule:: miniscope_io.uart_daq
:members:
:undoc-members:
```

9 changes: 9 additions & 0 deletions docs/api/vendor/index.md
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# Vendor

Modules that incorporate some proprietary/nonfree component and are vendored in

```{toctree}
:caption: Vendor
opalkelly
```
4 changes: 4 additions & 0 deletions docs/api/vendor/opalkelly.md
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# OpalKelly FrontPanel

(your docs on what this is for and how it works here!!!)

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'sphinx.ext.napoleon',
'sphinx.ext.autodoc',
'sphinxcontrib.autodoc_pydantic',
'sphinx.ext.intersphinx'
'sphinx.ext.intersphinx',
'sphinx.ext.todo'
]

templates_path = ['_templates']
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napoleon_attr_annotations = True

# graphviz
graphviz_output_format = "svg"
graphviz_output_format = "svg"


# autodoc
# Mock imports for packages we don't have yet - this one is
# for opal kelley stuff we need to figure out the licensing for
autodoc_mock_imports = ['routine']

# todo
todo_include_todos = True
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# Guide

```{toctree}
installation
```
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# Installation

From PyPI:

```bash
pip install miniscope_io
```

From git repository, using pip:
```bash
git clone https://github.com/Aharoni-Lab/miniscope-io
cd miniscope-io
pip install .
```

Or poetry:
```bash
git clone https://github.com/Aharoni-Lab/miniscope-io
cd miniscope-io
poetry install
```


## Additional Dependencies

### OpalKelly

`miniscope_io.vendor.opalkelly` - used for FPGA I/O

#### Linux

We package the OpalKelly FrontPanel SDK here, but it has an unadvertised dependency
on some system level packages:

- `liblua5.3-0`

So eg. on debian/ubuntu you'll need to:

```bash
apt install liblua5.3-0
```

#### Mac

No special installation should be required.

#### Windows

Currently windows is not implemented - see `miniscope_io/vencor/opalkelly/README.md` for
what was done to implement Linux and Mac to see what might need to be done here, pull requests welcome :)
13 changes: 12 additions & 1 deletion docs/index.md
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# miniscope-io

```{toctree}
:caption: Guide:
guide/index
```

```{toctree}
:maxdepth: 2
:caption: Contents:
api/index
changelog
```

```{toctree}
:caption: Meta:
meta/index
```


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# Meta


```{toctree}
changelog
todo
```

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# TODO

```{todolist}
```
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55 changes: 55 additions & 0 deletions miniscope_io/devices/opalkelly.py
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import time

from bitstring import BitArray

from miniscope_io.vendor import opalkelly as ok


class okDev(ok.okCFrontPanel):
"""
I/O and configuration for an (what kind of opal kelly device?)
.. todo::
Phil: document what this thing does, including how bitfiles work
and how they're generated/where they're located.
"""
def __init__(self, serial_id: str = ""):
super().__init__()
ret = self.OpenBySerial("")
if ret != self.NoError:
raise ValueError("Cannot open device: {}".format(serial_id))
self.info = ok.okTDeviceInfo()
ret = self.GetDeviceInfo(self.info)
if ret == self.NoError:
print("Connected to {}".format(self.info.productName))

def uploadBit(self, bit_file: str):

ret = self.ConfigureFPGA(bit_file)
if ret == self.NoError:
print("Succesfully uploaded {}".format(bit_file))
else:
raise ValueError("Configuration of {} failed".format(self.info.productName))
print(
"FrontPanel {} supported".format(
"is" if self.IsFrontPanelEnabled() else "not"
)
)
ret = self.ResetFPGA()

def readData(self, length: int, addr: int = 0xA0, blockSize: int = 16):
buf = bytearray(length)
ret = self.ReadFromBlockPipeOut(addr, data=buf, blockSize=blockSize)
if ret < 0:
raise ValueError("Read failed: {}".format(ret))
elif ret < length:
print("Only {} bytes read".format(ret))
return buf

def setWire(self, addr: int, val: int):
ret = self.SetWireInValue(addr, val)
ret = self.UpdateWireIns()
if ret != self.NoError:
raise ValueError("Wire update failed: {}".format(ret))
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