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1. AUC_Catelog AUC_Catelog Public

   This project was to create our designed AUC Catalog. It was divided into three phases; the first was to create the database design and the schema. The second phase was to scrape the original AUC ca…

   Python

2. FemtoRV32-Piplined-Processor FemtoRV32-Piplined-Processor Public

   The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

   Verilog 5 1

3. cpu_simulator cpu_simulator Public

   C++

4. MachineLearnig_ByAndrewNg_coursera MachineLearnig_ByAndrewNg_coursera Public

   Jupyter Notebook

5. vivid_team vivid_team Public

   it is a website for education platform demo which is for competition.

   JavaScript

6. risc_v_dissambler risc_v_dissambler Public

   This project is simply to convert binary(in Risc-v instruction-set architecture) to Risc-v assembly language

   C++ 1