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Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes

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Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
formal_verification		formal_verification
system_verilog		system_verilog
verilog		verilog
yosys		yosys
LICENSE		LICENSE
README.md		README.md

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RTL_Notes

Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes

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Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes

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Verilog 100.0%