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feat!: Brillig with a stack and conditional inlining #8989

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Oct 10, 2024
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c33685b
feat(avm): simulator relative addr
fcarreiro Sep 26, 2024
33e783a
feat: First implementation of a stack in brillig
sirasistant Sep 30, 2024
d9fb82d
make transpiler work altough wrongly
sirasistant Oct 1, 2024
288795a
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 1, 2024
a10965d
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 2, 2024
f2ef5d2
feat: add inline always annotations
sirasistant Oct 2, 2024
96b2e43
feat: conditional inlining
sirasistant Oct 3, 2024
2df690a
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 3, 2024
8e3c11a
add stack too deep check
sirasistant Oct 3, 2024
9354727
restore mov registers test
sirasistant Oct 3, 2024
14829f1
fix
sirasistant Oct 3, 2024
156114d
add test for stack auto compacting
sirasistant Oct 3, 2024
16af6d1
add test on relative addressing
sirasistant Oct 3, 2024
aadde7b
chore(avm)!: make indirects big enough for relative addressing
fcarreiro Oct 3, 2024
c1437c7
initial transpiler fixes
sirasistant Oct 3, 2024
3a30621
cpp side
fcarreiro Oct 3, 2024
1c08d8e
Merge branch 'fc/avm-big-enough-indirects' into arv/stack_implementation
sirasistant Oct 3, 2024
703e54b
fix
sirasistant Oct 3, 2024
0b142fa
remove ununsed operands
sirasistant Oct 3, 2024
9bd0874
fix(avm): MSM not including enough operands
fcarreiro Oct 3, 2024
33a90d8
update msm
sirasistant Oct 3, 2024
a153354
Merge branch 'fc/avm-fix-operands' into arv/stack_implementation
sirasistant Oct 3, 2024
1c8b907
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 4, 2024
ffd4add
fix some opcodes
sirasistant Oct 4, 2024
bb1d996
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 4, 2024
bfdf558
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 4, 2024
8663cda
comment changes
sirasistant Oct 4, 2024
8f7e84f
fix bad merge
sirasistant Oct 4, 2024
4b54943
fix unrolling
sirasistant Oct 4, 2024
2b63475
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 4, 2024
ba24b03
test: add test for inliner with different aggressiveness
sirasistant Oct 8, 2024
d713f37
use floats when aggregating weights
sirasistant Oct 8, 2024
ce9f1a3
refactor
sirasistant Oct 8, 2024
997f60c
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 8, 2024
c0f3fcd
oops!
sirasistant Oct 8, 2024
cb85533
inliner aggressiveness as i64
sirasistant Oct 8, 2024
ebdaed9
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 8, 2024
f466158
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 9, 2024
36bcb0f
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 9, 2024
f5fd1c3
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 9, 2024
801a6cb
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 10, 2024
14d527a
feat(avm): relative addressing in avm circuit (#9155)
jeanmon Oct 10, 2024
e0047f6
Merge branch 'master' into arv/stack_implementation
sirasistant Oct 10, 2024
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11 changes: 10 additions & 1 deletion avm-transpiler/src/bit_traits.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use acvm::{AcirField, FieldElement};
use acvm::{acir::brillig::MemoryAddress, AcirField, FieldElement};

fn get_msb(n: u128) -> usize {
let mut n = n;
Expand Down Expand Up @@ -56,6 +56,15 @@ impl BitsQueryable for usize {
}
}

impl BitsQueryable for MemoryAddress {
fn num_bits(&self) -> usize {
match self {
MemoryAddress::Direct(address) => get_msb(*address as u128),
MemoryAddress::Relative(offset) => get_msb(*offset as u128),
}
}
}

pub fn bits_needed_for<T: BitsQueryable>(val: &T) -> usize {
let num_bits = val.num_bits();
if num_bits <= 8 {
Expand Down
52 changes: 46 additions & 6 deletions avm-transpiler/src/instructions.rs
Original file line number Diff line number Diff line change
@@ -1,16 +1,11 @@
use std::fmt::{self, Display};
use std::fmt::{Debug, Formatter};

use acvm::acir::brillig::MemoryAddress;
use acvm::{AcirField, FieldElement};

use crate::opcodes::AvmOpcode;

/// Common values of the indirect instruction flag
pub const ALL_DIRECT: u8 = 0b00000000;
pub const ZEROTH_OPERAND_INDIRECT: u8 = 0b00000001;
pub const FIRST_OPERAND_INDIRECT: u8 = 0b00000010;
pub const SECOND_OPERAND_INDIRECT: u8 = 0b00000100;

/// A simple representation of an AVM instruction for the purpose
/// of generating an AVM bytecode from Brillig.
/// Note: this does structure not impose rules like "ADD instruction must have 3 operands"
Expand Down Expand Up @@ -141,3 +136,48 @@ impl AvmOperand {
}
}
}

#[derive(Debug, Default)]
pub(crate) struct AddressingModeBuilder {
indirect: Vec<bool>,
relative: Vec<bool>,
}

impl AddressingModeBuilder {
pub(crate) fn direct_operand(mut self, address: &MemoryAddress) -> Self {
self.relative.push(address.is_relative());
self.indirect.push(false);

self
}

pub(crate) fn indirect_operand(mut self, address: &MemoryAddress) -> Self {
self.relative.push(address.is_relative());
self.indirect.push(true);

self
}

pub(crate) fn build(self) -> AvmOperand {
let num_operands = self.indirect.len();
assert!(num_operands <= 8, "Too many operands for building addressing mode bytes");

let mut result = 0;
for (i, (indirect, relative)) in
self.indirect.into_iter().zip(self.relative.into_iter()).enumerate()
{
if indirect {
result |= 1 << i;
}
if relative {
result |= 1 << (num_operands + i);
}
}

if num_operands <= 4 {
AvmOperand::U8 { value: result as u8 }
} else {
AvmOperand::U16 { value: result as u16 }
}
}
}
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