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Fixup cycles on CPU and introduce LCD._cycles_to_frame
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Baekalfen committed Sep 21, 2024
1 parent 9acc6f3 commit 2a0db1a
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Showing 6 changed files with 11 additions and 4 deletions.
2 changes: 1 addition & 1 deletion pyboy/core/cpu.pxd
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ cdef class CPU:

cdef uint8_t interrupts_flag, interrupts_enabled, interrupts_flag_register, interrupts_enabled_register

cdef int64_t cycles_target, _cycles
cdef int64_t _cycles

cdef inline int check_interrupts(self) noexcept nogil
cdef void set_interruptflag(self, int) noexcept nogil
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4 changes: 4 additions & 0 deletions pyboy/core/cpu.py
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ def save_state(self, f):
f.write(self.interrupts_enabled_register)
f.write(self.interrupt_queued)
f.write(self.interrupts_flag_register)
f.write_64bit(self._cycles)

def load_state(self, f, state_version):
self.A, self.F, self.B, self.C, self.D, self.E = [f.read() for _ in range(6)]
Expand All @@ -70,6 +71,8 @@ def load_state(self, f, state_version):
if state_version >= 8:
self.interrupt_queued = f.read()
self.interrupts_flag_register = f.read()
if state_version >= 12:
self._cycles = f.read_64bit()
logger.debug("State loaded: %s", self.dump_state(""))

def dump_state(self, sym_label):
Expand Down Expand Up @@ -132,6 +135,7 @@ def tick(self, cycles_target):
self._cycles += self.fetch_and_execute()
if self.bail: # Possible cycles-target changes
break

return self._cycles - _cycles0

def check_interrupts(self):
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2 changes: 1 addition & 1 deletion pyboy/core/lcd.pxd
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ cdef class LCD:
cdef PaletteRegister OBP1
cdef Renderer renderer
cdef uint8_t[144][5] _scanlineparameters
cdef int64_t _cycles_to_interrupt
cdef int64_t _cycles_to_interrupt, _cycles_to_frame

@cython.locals(interrupt_flag=uint8_t,bx=int,by=int,wx=int,wy=int)
cdef uint8_t tick(self, int) noexcept nogil
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3 changes: 3 additions & 0 deletions pyboy/core/lcd.py
Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,7 @@ def __init__(self, cgb, cartridge_cgb, color_palette, cgb_color_palette, randomi
self.cgb = cgb
self._scanlineparameters = [[0, 0, 0, 0, 0] for _ in range(ROWS)]
self._cycles_to_interrupt = 0
self._cycles_to_frame = FRAME_CYCLES

if self.cgb:
# Setting for both modes, even though CGB is ignoring them. BGP[0] used in scanline_blank.
Expand Down Expand Up @@ -204,6 +205,7 @@ def tick(self, cycles):
self.renderer.blank_screen(self)

self._cycles_to_interrupt = self.clock_target - self.clock
self._cycles_to_frame = self.clock - FRAME_CYCLES
return interrupt_flag

def save_state(self, f):
Expand Down Expand Up @@ -294,6 +296,7 @@ def load_state(self, f, state_version):

self.clock = f.read_64bit()
self.clock_target = f.read_64bit()
self._cycles_to_frame = self.clock - FRAME_CYCLES
self.next_stat_mode = f.read()

if self.cgb:
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2 changes: 1 addition & 1 deletion pyboy/core/mb.py
Original file line number Diff line number Diff line change
Expand Up @@ -296,12 +296,12 @@ def tick(self):
min(
self.timer._cycles_to_interrupt,
self.lcd._cycles_to_interrupt, # TODO: Be more agreesive. Only if actual interrupt enabled.
self.lcd._cycles_to_frame,
self.sound._cycles_to_interrupt, # TODO: Not implemented
# self.serial.cycles_to_interrupt(),
mode0_cycles
)
)
# cycles_target = 4
cycles = self.cpu.tick(cycles_target)

#TODO: Support General Purpose DMA
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2 changes: 1 addition & 1 deletion pyboy/utils.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@

__all__ = ["WindowEvent", "dec_to_bcd", "bcd_to_dec"]

STATE_VERSION = 11
STATE_VERSION = 12

##############################################################
# Buffer classes
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