Skip to content

Verilog implementation of a 5-stage RISC-V based processor

License

Notifications You must be signed in to change notification settings

Beanavil/Abejaruco

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Abejaruco

What is this?

Get started

Dependencies

  • iverilog
    • gperf
  • verilator

iverilog

Download as described in https://github.com/steveicarus/iverilog.

Configure

The project uses CMake as buildsystem. To configure the project using the system packages use

cmake -G Ninja -B build -S .

If you want CMake to download the necessary dependencies, use

cmake -G Ninja -B build -S . -DDEPENDENCIES_FORCE_DOWNLOAD=ON

Build

Once the project is configured, just run

cmake --build build --clean-first

Contribute

Please refer to the Contributing Guidelines.

About

Verilog implementation of a 5-stage RISC-V based processor

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published