NASSCOM-VSD-SoC-Design-and-Planning

What is an RTL to GDSII flow?

Register Transfer Language (RTL) to Graphic Data System II (GDSII) is a comprehensive design flow in integrated circuit (IC) development that transforms a high-level hardware description into a physical layout ready for fabrication in the foundry. The RTL to GDSII process flows through several steps starting from the RTL design, where the circuit's functionality is coded into the hardware description languages using Verilog or VHDL. This RTL code is then converted into a gate-level netlist through a process called synthesis. Once the netlist is created, the first step in the physical design process is floorplanning followed by placement, clock-tree synthesis (CTS), and routing. After placement and routing, signoff checks including Design Rule Checking (DRC), Layout Versus Schematic (LVS) checks, and Static Timing Analysis (STA) are performed. The whole process is iterative until power, performance, and area targets are not met. This process is called Place and Route (PnR). Finally, the design is exported as a GDSII file, which is used by semiconductor foundries to fabricate the physical ICs from the GDSII layout. A simplified RTL to GDSII process flow is shown below: Introduction to Openlane flow OpenLANE is a completely automated RTL to GDSII design flow that includes open-source tools and custom scripts for design optimization. Openlane is built around Skywater 130nm process node and is capable of performing full ASIC implementation steps from RTL down to GDSII. The flow-chart below gives a complete openlane design flow from RTL to GDSII Overview of Physical Design flow In ASIC design flow, PnR is the core which consists of several steps. Below are the stages and the respective tools used by OpenLANE:

• Synthesis: Generates gate-level netlist, performs cell mapping, and pre-layout STA.
• Floorplanning: During this step some major decisions are taken like how to partition the system into the subsystems and blocks, how to arrange the blocks on the chip, where to allocate the stdcells, macros, memory, etc. During floorplanning the IO cell and power planning takes place.
• Placement: Placement steps decide the location of stdcells in the design. In this step, the wire length is estimated and therefore placement takes place considering the estimated wire lengths.
• Clock-tree synthesis (CTS): In this step clock tree netlist is implemented, which includes buffers, and the wiring of the clock network is performed. The objective of this step is to minimize the skew and minimize power dissipation.
• Routing (Global and Detailed): Routing creates the wiring layout for all nets other than the clock and power supply. The routing is divided into GLOBAL ROUTING and DETAILED ROUTING. Global routing is the planning stage, where a routing plan for a given net is created by dividing the entire routing region into rectangular tiles or bins. The detailed router decides the actual routing of each pre-assigned globals bins, where the actual wires and vias are created

Microcontroller Board Components

Core: Definition: The central processing unit (CPU) of the microcontroller that executes instructions. Example: ARM Cortex-M, RISC-V core. Die:

Pad: Definition: The physical connection points on the microcontroller chip where external components are connected.

GPIO (General-Purpose Input/Output): Definition: Pins on the microcontroller that can be programmed to either input signals (e.g., sensors) or output signals (e.g., LEDs).

Bank: Definition: A grouping of I/O pins or memory segments used for organization within the microcontroller. For GPIO, it refers to a set of pins grouped together.

Foundries: Definition: Facilities where the microcontroller chips are manufactured. Examples include TSMC, Intel.

IPs (Intellectual Properties): Definition: Pre-designed blocks of logic that can be integrated into the microcontroller. Examples include UART, SPI, and I2C controllers.

SRAM (Static Random-Access Memory): Definition: A type of volatile memory used for temporary data storage within the microcontroller. Fast but more expensive and power-consuming than DRAM.

DRAM (Dynamic Random-Access Memory): Definition: A type of volatile memory used for larger, temporary data storage. Requires periodic refreshing to maintain data.

ADC (Analog-to-Digital Converter): Definition: Converts analog signals (e.g., sensor outputs) into digital values that can be processed by the microcontroller.

DAC (Digital-to-Analog Converter): Definition: Converts digital values into analog signals (e.g., to drive speakers or analog displays).

RISC-V SoC (System on Chip): Definition: A microcontroller or microprocessor incorporating a RISC-V core along with additional integrated components such as memory, peripherals, and communication interfaces.

Macros: Definition: Predefined sequences of code or hardware configurations used to simplify and automate repetitive tasks in programming or hardware design.

Connecting All Components Core: Executes instructions and processes data. Die: Houses the core and other integrated components. Pad: Connects the die to external components via GPIO. GPIO: Interfaces with external devices, configured via macros. Bank: Organizes GPIO and other resources. Foundries: Manufacture the microcontroller with the integrated core, SRAM, DRAM, ADC, DAC, and IPs. IPs: Provide specialized functions like UART and SPI, integrated into the SoC. SRAM & DRAM: Store data temporarily for processing and operation. ADC & DAC: Enable analog signal processing and generation. This layout ensures a microcontroller can interact with the external world and perform complex tasks by integrating various components into a single, functional chip.

LAB 1:GETTING FAMILIAR WITH OPENLANE EDA TOOLS

__Design Preparation Step:

• docker
• ./flow.tcl -interactive
• package require openlane 0.9
• prep -design picorv32a
• To view the latest directory created : /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs

command to run synthesis: run_synthesis

Review files after design prep and run synthesis

Synthesis Report

Characterization of Synthesized Results

LAB 2: FLOORPLANNING & PLACEMENT

command to run floorplan : run_floorplan

1. def file of floorplan

Command to run floorplan in magic -T

# Change directory to path containing generated floorplan def
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/29-07_10-25/results/floorplan/

# Command to load the floorplan def in magic tool
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

2. View of floorplan in magic -T

LAB 3: Placement in openlane

Run 'picorv32a' design congestion aware placement using OpenLANE flow and generate necessary outputs run_placement

Load placement.def in magic layout

# Change directory to path containing generated placement def
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/29-07_10-25/results/placement/
# Command to load the placement def in magic tool
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

HOW TO MAKE CHANGES WHILE BEING IN THE FLOW?

One can change the floorplan variables like core utilization and IO mode Example : TO CHANGE THE IO pins alignment in the layout, first we can verify the current configuration of the Pins, Go to the following directory as shown in the image below: /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/26-07_10-33/results/floorplan

Then use the command to open the '.def' file in magic: ` magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def

Steps to get clone of git "vsdstdcelldesign" repo The repository "vsdstdcelldesign" contains the .mag file for the inverter and spice models for sky130 nmos/pmos transistors.

Got to the openlane directory and run the following command to clone the git repository:

git clone https://github.com/nickson-jose/vsdstdcelldesign.git

Now, we will open the .mag file and to do that we require the sky130A.tech file from the following directory:

/home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic

we copy the file using the following command

cp sky130A.tech /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign

Now, open the sky130_inv.mag file in magic:

magic -T sky130A.tech sky130_inv.mag &

EXTRACT THE SPICE NETLIST IN MAGIC

Spice file created:

CREATING FINAL SPICE DECK USING SKY130 TECH

Now to simulate in ngspice, use the following command while in the 'vsdstdcelldesign' directory:

ngspice sky130_inv.spice

Now, to open the plot use plot y vs time a in the ngspice terminal

Inverter Output Values:

CHARACTERIZATION OF INVERTER USING SKY130 TECH FILES

CHARACTERIZE INVERTER USING SKY130 TECH FILES To characterize the inverter, we analyze the ngspice plot and determined the following parameters:

Rise Time: The time for the output waveform to transition from 20% to 80% of its maximum value. From plot points: (x0 = 2.18192ns, y0 = 0.66049) to (x0 = 2.24571ns, y0 = 2.64018). Calculated Rise Time = 0.0634 ns

Fall Time: The time for the output waveform to transition from 80% to 20% of its maximum value. From plot points: (x0 = 4.0525ns, y0 = 2.63976) to (x0 = 4.09516ns, y0 = 0.659249). Calculated Fall Time = 0.0422 ns

Propagation Delay(Cell Rise Delay): The time for the output to transition 50% in response to a 50% change at the input. From plot points: Input(x0 = 2.15018ns, y0 = 1.65018) to Output(x0 = 2.21088ns, y0 = 1.65). Calculated Propagation Delay = 0.064 ns

Cell Fall Delay: The delay for the output to transition 50% due to a 50% change at the input. From plot points: (x0 = 4.04997ns, y0 = 1.65) to (x0 = 4.07748ns, y0 = 1.65). Calculated Cell Fall Delay = 0.0277 ns

We have now characterized the inverter cell for a room temperature of 27 degC. Similarly, this cell can be characterized for different process, voltage, and temperature (PVT) corners to fully characterize this cell for different PVT corners.

With these parameters successfully characterized, the next step is to create a LEF file from this cell, which will be plugged into openlane picorv32a design flow.

INTRODUCTION TO MAGIC TOOL AND DRC RULES

sudo wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz

Once downloaded the zip file we extract it using the command sudo tar xfz drc_tests.tgz

FIXING POLY.9 ERROR IN SKY120 TECH FILE

FIXING NWELL CHALLENGES

LAB 4: PRE-LAYOUT TIMING ANALYSIS & IMPORTANCE OF GOOD CLOCK TREE

Open the file name tracks.info. This file specifies pitch, spacing, and other relevant details necessary for efficient routing. Each metal layer has an X and Y direction.

/home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd less tracks.info

Increased Grid size:

Converting magic layout to standard cell LEF

Port class and port use attributes for a layout: After port definition, the next step is setting port class and port use attributes. These attributes are used to define the purpose of the port. Class and use properties are used by the LEF format for read-and-write routines. Press the button "s" to select the right port layer, then use the following commands:

Creating lef file:

Generated lef file in vsdstdcelldesign:

Introduction to timing libs and steps to include new cell in the synthesis

/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign cp sky130_vsdinv.lef /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src For the synthesis step, we need the std cell library files. Therefore we copy the .lib files from the directory vsdstdcelldesign/libs using the following commands: cp sky130_fd_sc_hd__* /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src

Now, we need to modify the config.tcl file: Go to the picorv32a directory and open the file using vim and we make the following modifications:

Now, invoke the docker and perform the regular steps

./flow.tcl -interactive
package require openlane 0.9

#to continue the work in the already made directory in the runs folder
prep -design picorv32a -tag 14-08_14-23 -overwrite

Synthesis result for custom cell:

Reduced Slack time for synthesis:

Now, to check whether the std cell we have created has been included in the design or not. Go to the following directory: /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/26-07_10-33/results/placement then magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

Timing analysis with ideal clocks using openSTA

Configure OpenSTA for post-synth timing analysis

my_base file for STA:

Slack met:

Clock tree synthesis TritonCTS and signal integrity

write_verilog //path of the previous design//
#In our case:
write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/20-07_16-44/results/synthesis/picorv32a.synthesis.v

Synthesis file overwritten by verilog command:

Run floorplan, placement and CTS

init_floorplan
place_io
tap_decap_or

run_cts

CTS result:

Generated cts file:

Post cts Result:

Run openlaneflow synthesis with modified command to improve timing

# Change directory to openlane flow directory
cd Desktop/work/tools/openlane_working_dir/openlane
docker

# Now that we have entered the OpenLANE flow contained docker sub-system we can invoke the OpenLANE flow in the Interactive mode using the following command
./flow.tcl -interactive

# Now that OpenLANE flow is open we have to input the required packages for proper functionality of the OpenLANE flow
package require openlane 0.9

# Now the OpenLANE flow is ready to run any design and initially we have to prep the design creating some necessary files and directories for running a specific design which in our case is 'picorv32a'
prep -design picorv32a

# Adiitional commands to include newly added lef to openlane flow
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs

# Command to set new value for SYNTH_SIZING
set ::env(SYNTH_SIZING) 1

# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesis
![post CTS](https://github.com/user-attachments/assets/43650b5a-2002-419e-9fb3-2e4d16ffcdfe)

# Change directory to openlane
cd Desktop/work/tools/openlane_working_dir/openlane

# Command to invoke OpenSTA tool with script
sta pre_sta.conf

Include new lef

# Now the OpenLANE flow is ready to run any design and initially we have to prep the design creating some necessary files and directories for running a specific design which in our case is 'picorv32a'
prep -design picorv32a -tag 29-07_10-25 -overwrite

# Adiitional commands to include newly added lef to openlane flow
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs

# Command to set new value for SYNTH_SIZING
set ::env(SYNTH_SIZING) 1

# Command to set new value for SYNTH_MAX_FANOUT
set ::env(SYNTH_MAX_FANOUT) 4

# Command to display current value of variable SYNTH_DRIVING_CELL to check whether it's the proper cell or not
echo $::env(SYNTH_DRIVING_CELL)

# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesis
# Change directory to openlane
cd Desktop/work/tools/openlane_working_dir/openlane

# Command to invoke OpenSTA tool with script
sta pre_sta.conf

Timing analysis with real clocks using openSTA

Post cts OPENROAD TIMING analyis

# Command to run OpenROAD tool
openroad

# Reading lef file
read_lef /openLANE_flow/designs/picorv32a/runs/29-07_10-25/tmp/merged.lef

# Reading def file
read_def /openLANE_flow/designs/picorv32a/runs/29-07_10-25/results/cts/picorv32a.cts.def

# Creating an OpenROAD database to work with
write_db pico_cts.db

# Loading the created database in OpenROAD
read_db pico_cts.db

# Read netlist post CTS
read_verilog /openLANE_flow/designs/picorv32a/runs/29-07_10-25/results/synthesis/picorv32a.synthesis_cts.v

# Read library for design
read_liberty $::env(LIB_SYNTH_COMPLETE)

# Link design and library
link_design picorv32a

# Read in the custom sdc we created
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc

# Setting all cloks as propagated clocks
set_propagated_clock [all_clocks]

# Check syntax of 'report_checks' command
help report_checks

# Generating custom timing report
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

# Exit to OpenLANE flow
exit

opening openroad:

Slack hold time satisfied:

Slack setup time satisfied:

Adding back the sky file:

####### LAB 5: FINAL STEPS FOR RTL2GDS USING TRITONROUTE & OPENSTA Once CTS is ready we can generate a power distribution network (PDN) before routing. Let's check our current DEF file, using the following commands:

echo $::env(CURRENT_DEF)

use the PDN command: gen_pdn

The PDN output above shows that PDN writes the LEF file, reads the CTS DEF and creates the grid and straps for the power and ground. As we know STDcells are placed in the std rows, therefore STDcell power rails are placed along the stdcell rows. The stdcell rails have a pitch of 2.720, equivalent to the height of the stdcell inverter. Thus the power and ground stdcell rails match with the GND and PWR ports of stdcell inverter.

The diagram below shows power planning.

In the figure above, the green area corresponds to the picorv32a design. The red pads are for power, while the blue pads provide the ground connection.

From the pads, power is supplied to the rectangular close-loop rings. The vertical lines connected to the rings are power straps. The stdcells power and ground rails are attached to vertical straps. The height of the std cells must be multiple of the rail pitch to ensure proper power and ground connection. This image shows how the power comes from the outside to the pads, pads to the rings, rings to strap/stripe, and strap/stripe to stdcell rows.

Global and detail routing and configure TritonRoute

# Check value of 'CURRENT_DEF'
echo $::env(CURRENT_DEF)

# Check value of 'ROUTING_STRATEGY'
echo $::env(ROUTING_STRATEGY)

# Command for detailed route using TritonRoute
run_routing
Screenshots of routing run

Commands to load routed def in magic in another terminal

# Change directory to path containing routed def
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/05-08_13-22/results/routing/

# Command to load the routed def in magic tool
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.def &

References

https://github.com/nickson-jose/vsdstdcelldesign

https://skywater-pdk.readthedocs.io/en/main/index.html