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Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them

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Name		Name	Last commit message	Last commit date
Latest commit History 33 Commits
combinational		combinational
cpu		cpu
memory		memory
other/MatrixMultiplier		other/MatrixMultiplier
sequential		sequential
signal_processing/FirFilter		signal_processing/FirFilter
.gitignore		.gitignore
LICENSE		LICENSE
Readme.md		Readme.md
setup_clash.sh		setup_clash.sh

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Bunch of circuits in Verilog and in Clash to learn and compare them

Combinational

Sequential

Memory

Ring buffer (FIFO)

Digital Signal Processing

FIR filter

CPU

CPU in Clash based on my older verilog design (VeriRISCy)

Others

Matrix multiplier

Steps to run:

I am running Clash in minimal setup with clashi.

Setup clash by running setup_clash.sh. This need to be run only once.
Run run.sh in a desired project and follow the instructions there

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Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them

haskell verilog clash-lang

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