s/EdgeKind::Const/EdgeKind::Static/

src/builder/build_traits.rs

@@ -603,7 +603,7 @@ enum ValueKind {
 fn get_value_kind(base: &Hugr, src: Node, src_offset: Port) -> ValueKind {
  let wire_kind = base.get_optype(src).port_kind(src_offset).unwrap();
  match wire_kind {
- EdgeKind::Const(_) => ValueKind::Const,
+ EdgeKind::Static(_) => ValueKind::Const,
  EdgeKind::Value(simple_type) => match simple_type {
  SimpleType::Classic(_) => ValueKind::Classic,
  SimpleType::Linear(typ) => ValueKind::Linear(typ),

src/hugr.rs

@@ -114,7 +114,7 @@ impl Hugr {
  let optype = self.op_types.get(node);
  let offset = self.graph.port_offset(port).unwrap();
  match optype.port_kind(offset).unwrap() {
- EdgeKind::Const(ty) => {
+ EdgeKind::Static(ty) => {
  PortStyle::new(html_escape::encode_text(&format!("{}", ty)))
  }
  EdgeKind::Value(ty) => {

src/hugr/rewrite/simple_replace.rs

@@ -86,7 +86,7 @@ impl Rewrite for SimpleReplacement {
  .replacement
  .get_optype(node)
  .signature()
- .const_input
+ .static_input
  .is_empty()
  {
  return Err(SimpleReplacementError::InvalidReplacementNode());

src/hugr/validate.rs

@@ -225,10 +225,16 @@ impl<'a> ValidationContext<'a> {
  let port_kind = optype.port_kind(port).unwrap();
  let dir = port.direction();
 
- // Input ports and output linear ports must always be connected
  let mut links = self.hugr.graph.port_links(port_index).peekable();
  let must_be_connected = match dir {
- Direction::Incoming => port_kind.is_linear() || matches!(port_kind, EdgeKind::Const(_)),
+ // Incoming ports must be connected, except for state order ports, branch case nodes,
+ // and CFG nodes.
+ Direction::Incoming => {
+ port_kind != EdgeKind::StateOrder
+ && port_kind != EdgeKind::ControlFlow
+ && optype.tag() != OpTag::Case
+ }
+ // Linear dataflow values must be connected.
  Direction::Outgoing => port_kind.is_linear(),
  };
  if must_be_connected && links.peek().is_none() {
@@ -470,7 +476,7 @@ impl<'a> ValidationContext<'a> {
 
  match from_optype.port_kind(from_offset).unwrap() {
  // Inter-graph constant wires do not have restrictions
- EdgeKind::Const(typ) => {
+ EdgeKind::Static(typ) => {
  if let OpType::Const(ops::Const(val)) = from_optype {
  return typecheck_const(&typ, val).map_err(ValidationError::from);
  } else {

src/ops/constant.rs

@@ -32,7 +32,7 @@ impl OpTrait for Const {
  }
 
  fn other_output(&self) -> Option<EdgeKind> {
- Some(EdgeKind::Const(self.0.const_type()))
+ Some(EdgeKind::Static(self.0.const_type()))
  }
 }
 

src/ops/custom.rs

@@ -148,7 +148,7 @@ impl OpDef {
  ) -> Self {
  let inputs: Vec<_> = port_names
  .input_zip(&signature)
- .chain(port_names.const_input_zip(&signature))
+ .chain(port_names.static_input_zip(&signature))
  .map(|(n, t)| (Some(n.clone()), t.clone()))
  .collect();
 

src/ops/dataflow.rs

@@ -168,7 +168,7 @@ impl DataflowOpTrait for Call {
 
  fn signature(&self) -> Signature {
  Signature {
- const_input: vec![ClassicType::graph_from_sig(self.signature.clone()).into()].into(),
+ static_input: vec![ClassicType::graph_from_sig(self.signature.clone()).into()].into(),
  ..self.signature.clone()
  }
  }

src/ops/module.rs

@@ -44,7 +44,7 @@ impl OpTrait for Def {
  }
 
  fn other_output(&self) -> Option<EdgeKind> {
- Some(EdgeKind::Const(ClassicType::graph_from_sig(
+ Some(EdgeKind::Static(ClassicType::graph_from_sig(
  self.signature.clone(),
  )))
  }
@@ -71,7 +71,7 @@ impl OpTrait for Declare {
  }
 
  fn other_output(&self) -> Option<EdgeKind> {
- Some(EdgeKind::Const(ClassicType::graph_from_sig(
+ Some(EdgeKind::Static(ClassicType::graph_from_sig(
  self.signature.clone(),
  )))
  }

src/types.rs

@@ -27,8 +27,8 @@ pub enum EdgeKind {
  ControlFlow,
  /// Data edges of a DDG region, also known as "wires".
  Value(SimpleType),
- /// A reference to a constant value definition, used in the module region.
- Const(ClassicType),
+ /// A reference to a static value definition.
+ Static(ClassicType),
  /// Explicitly enforce an ordering between nodes in a DDG.
  StateOrder,
  /// An edge specifying a resource set.
@@ -46,16 +46,16 @@ impl EdgeKind {
 }
 
 /// Describes the edges required to/from a node. This includes both the concept of "signature" in the spec,
-/// and also the target (value) of a call (constant).
+/// and also the target (value) of a call (static).
 #[cfg_attr(feature = "pyo3", pyclass)]
 #[derive(Clone, Default, Debug, PartialEq, Eq, serde::Serialize, serde::Deserialize)]
 pub struct Signature {
  /// Value inputs of the function.
  pub input: TypeRow,
  /// Value outputs of the function.
  pub output: TypeRow,
- /// Possible constE input (for call / load-constant).
- pub const_input: TypeRow,
+ /// Possible static input (for call / load-constant).
+ pub static_input: TypeRow,
  /// The resource requirements of all the inputs
  pub input_resources: ResourceSet,
  /// The resource requirements of all the outputs
@@ -67,7 +67,7 @@ impl Signature {
  /// The number of wires in the signature.
  #[inline(always)]
  pub fn is_empty(&self) -> bool {
- self.const_input.is_empty() && self.input.is_empty() && self.output.is_empty()
+ self.static_input.is_empty() && self.input.is_empty() && self.output.is_empty()
  }
 
  /// Returns whether the data wires in the signature are purely linear.
@@ -103,12 +103,12 @@ impl Signature {
  /// Returns the type of a [`Port`]. Returns `None` if the port is out of bounds.
  pub fn get(&self, port: Port) -> Option<EdgeKind> {
  if port.direction() == Direction::Incoming && port.index() >= self.input.len() {
- self.const_input
+ self.static_input
  .get(port.index() - self.input.len())?
  .clone()
  .try_into()
  .ok()
- .map(EdgeKind::Const)
+ .map(EdgeKind::Static)
  } else {
  self.get_df(port).cloned().map(EdgeKind::Value)
  }
@@ -134,22 +134,22 @@ impl Signature {
  }
  }
 
- /// Returns the number of value and const ports in the signature.
+ /// Returns the number of value and static ports in the signature.
  #[inline]
  pub fn port_count(&self, dir: Direction) -> usize {
  match dir {
- Direction::Incoming => self.input.len() + self.const_input.len(),
+ Direction::Incoming => self.input.len() + self.static_input.len(),
  Direction::Outgoing => self.output.len(),
  }
  }
 
- /// Returns the number of input value and const ports in the signature.
+ /// Returns the number of input value and static ports in the signature.
  #[inline]
  pub fn input_count(&self) -> usize {
  self.port_count(Direction::Incoming)
  }
 
- /// Returns the number of output value and const ports in the signature.
+ /// Returns the number of output value and static ports in the signature.
  #[inline]
  pub fn output_count(&self) -> usize {
  self.port_count(Direction::Outgoing)
@@ -215,12 +215,12 @@ impl Signature {
  pub fn new(
  input: impl Into<TypeRow>,
  output: impl Into<TypeRow>,
- const_input: impl Into<TypeRow>,
+ static_input: impl Into<TypeRow>,
  ) -> Self {
  Self {
  input: input.into(),
  output: output.into(),
- const_input: const_input.into(),
+ static_input: static_input.into(),
  input_resources: ResourceSet::new(),
  output_resources: ResourceSet::new(),
  }
@@ -240,12 +240,12 @@ impl Signature {
 
 impl Display for Signature {
  fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
- let has_inputs = !(self.const_input.is_empty() && self.input.is_empty());
+ let has_inputs = !(self.static_input.is_empty() && self.input.is_empty());
  if has_inputs {
  self.input.fmt(f)?;
- if !self.const_input.is_empty() {
+ if !self.static_input.is_empty() {
  f.write_char('<')?;
- display_list(&self.const_input, f)?;
+ display_list(&self.static_input, f)?;
  f.write_char('>')?;
  }
  f.write_str(" -> ")?;
@@ -264,16 +264,16 @@ pub struct SignatureDescription {
  pub input: Vec<SmolStr>,
  /// Output of the function.
  pub output: Vec<SmolStr>,
- /// Constant data references used by the function.
- pub const_input: Vec<SmolStr>,
+ /// Static data references used by the function.
+ pub static_input: Vec<SmolStr>,
 }
 
 #[cfg_attr(feature = "pyo3", pymethods)]
 impl SignatureDescription {
  /// The number of wires in the signature.
  #[inline(always)]
  pub fn is_empty(&self) -> bool {
- self.const_input.is_empty() && self.input.is_empty() && self.output.is_empty()
+ self.static_input.is_empty() && self.input.is_empty() && self.output.is_empty()
  }
 }
 
@@ -282,12 +282,12 @@ impl SignatureDescription {
  pub fn new(
  input: impl Into<Vec<SmolStr>>,
  output: impl Into<Vec<SmolStr>>,
- const_input: impl Into<Vec<SmolStr>>,
+ static_input: impl Into<Vec<SmolStr>>,
  ) -> Self {
  Self {
  input: input.into(),
  output: output.into(),
- const_input: const_input.into(),
+ static_input: static_input.into(),
  }
  }
 
@@ -338,12 +338,12 @@ impl SignatureDescription {
  Self::row_zip(&signature.output, &self.output)
  }
 
- /// Iterate over the constant input wires of the signature and their names.
- pub fn const_input_zip<'a>(
+ /// Iterate over the static input wires of the signature and their names.
+ pub fn static_input_zip<'a>(
  &'a self,
  signature: &'a Signature,
  ) -> impl Iterator<Item = (&SmolStr, &SimpleType)> {
- Self::row_zip(&signature.const_input, &self.const_input)
+ Self::row_zip(&signature.static_input, &self.static_input)
  }
 }