fix mypy

CQCL · Oct 10, 2024 · 9bbfffd · 9bbfffd
1 parent 1f8cddb
commit 9bbfffd
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/pytket/qir/conversion/profileqirgenerator.py b/pytket/qir/conversion/profileqirgenerator.py
@@ -210,9 +210,9 @@ def set_ssa_vars(self, reg_name: str, ssa_i64: Value, trunc: bool) -> None:
             ssa_i64_zext = self.module.module.builder.zext(
                 ssa_i_trunc, self.qir_int_type
             )
-            self.ssa_vars[reg_name].append((ssa_i64_zext, self.active_block))  # type: ignore
+            self.ssa_vars[reg_name].append((ssa_i64_zext, self.active_block))
         else:
-            self.ssa_vars[reg_name].append((ssa_i64, self.active_block))  # type: ignore
+            self.ssa_vars[reg_name].append((ssa_i64, self.active_block))
         self.list_of_changed_cregs.append(reg_name)
 
     def _reg2ssa_var(self, bit_reg: BitRegister) -> Value:
@@ -224,7 +224,7 @@ def _reg2ssa_var(self, bit_reg: BitRegister) -> Value:
                     f"Classical register should only have the size of {self.int_size}"
                 )
             ssa_var = pyqir.const(self.qir_int_type, 0)
-            self.ssa_vars[reg_name] = [(ssa_var, self.active_block)]  # type: ignore
+            self.ssa_vars[reg_name] = [(ssa_var, self.active_block)]
             return ssa_var
         else:
             return cast(Value, self.ssa_vars[reg_name])