Merge pull request #139 from CQCL/release/0.11.0

Release/0.11.0
CQCL · May 17, 2024 · d52db11 · d52db11
2 parents 0949278 + d2f4869
commit d52db11
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Showing 6 changed files with 119 additions and 5 deletions.
diff --git a/_metadata.py b/_metadata.py
@@ -1,2 +1,2 @@
-__extension_version__ = "0.10.1"
+__extension_version__ = "0.11.0"
 __extension_name__ = "pytket-qir"
diff --git a/docs/changelog.rst b/docs/changelog.rst
@@ -1,6 +1,12 @@
 Changelog
 ~~~~~~~~~
 
+0.11.0 (May 2024)
+-----------------
+
+* Updated pytket version requirement to 1.28.
+* add support for BitWiseOp.ONE, BitWiseOp.ZERO in conversion
+
 0.10.1 (April 2024)
 -------------------
 

diff --git a/pytket/qir/conversion/conversion.py b/pytket/qir/conversion/conversion.py
@@ -43,9 +43,11 @@
     BitAnd,
     BitEq,
     BitNeq,
+    BitOne,
     BitOr,
     BitWiseOp,
     BitXor,
+    BitZero,
     RegAdd,
     RegAnd,
     RegEq,
@@ -97,6 +99,11 @@
     BitEq: lambda b: partial(b.icmp, IntPredicate.EQ),
 }
 
+_TK_CLOPS_TO_PYQIR_BIT_NO_PARAM: dict = {
+    BitOne: 1,
+    BitZero: 0,
+}
+
 
 class QirGenerator:
     """Generate QIR from a pytket circuit."""
@@ -555,7 +562,7 @@ def _get_ssa_from_cl_bit_op(
 
             return output_instruction  # type: ignore
         else:
-            raise ValueError(f"unsupported bisewise operation {type(bit)}")
+            raise ValueError(f"unsupported bitwise operation {type(bit)}")
 
     def get_wasm_sar(self) -> dict[str, str]:
         return self.wasm_sar_dict
@@ -898,6 +905,15 @@ def condition_block() -> None:
                         module.builder
                     )(ssa_left, ssa_right)
 
+                elif type(op.get_exp()) in _TK_CLOPS_TO_PYQIR_BIT_NO_PARAM:
+                    # classical ops without parameters
+                    output_instruction = pyqir.const(
+                        self.qir_bool_type,
+                        _TK_CLOPS_TO_PYQIR_BIT_NO_PARAM[type(op.get_exp())],
+                    )
+                    returntypebool = True
+                    result_index = command.args[-1].index[0]
+
                 elif type(op.get_exp()) in _TK_CLOPS_TO_PYQIR_BIT:
                     # classical ops acting on bits returning bit
                     ssa_left = cast(  # type: ignore
@@ -911,7 +927,7 @@ def condition_block() -> None:
 
                     # add function to module
                     returntypebool = True
-                    result_index = command.args[-1].index[0]  # todo
+                    result_index = command.args[-1].index[0]
                     output_instruction = _TK_CLOPS_TO_PYQIR_BIT[type(op.get_exp())](
                         module.builder
                     )(ssa_left, ssa_right)

diff --git a/setup.py b/setup.py
@@ -31,7 +31,7 @@
     name="pytket-qir",
     version=metadata["__extension_version__"],
     author="TKET development team",
-    author_email="tket-support@cambridgequantum.com",
+    author_email="tket-support@quantinuum.com",
     python_requires=">=3.10",
     project_urls={
         "Documentation": "https://tket.quantinuum.com/extensions/pytket-qir/index.html",
@@ -45,7 +45,7 @@
     packages=find_namespace_packages(include=["pytket.*"]),
     include_package_data=True,
     install_requires=[
-        "pytket ~= 1.27",
+        "pytket ~= 1.28",
         "pyqir == 0.10.0",
     ],
     classifiers=[

diff --git a/tests/conditional_test.py b/tests/conditional_test.py
@@ -24,6 +24,7 @@
     if_not_bit,
     reg_eq,
 )
+from pytket.circuit.logic_exp import BitWiseOp, create_bit_logic_exp
 from pytket.qir.conversion.api import QIRFormat, pytket_to_qir
 
 
@@ -262,6 +263,25 @@ def test_pytket_qir_conditional_11() -> None:
     check_qir_result(result, "test_pytket_qir_conditional_11")
 
 
+def test_pytket_qir_conditional_12() -> None:
+    # test conditional with no register
+
+    circ = Circuit(7, name="testcirc")
+
+    exp = create_bit_logic_exp(BitWiseOp.ONE, [])
+    circ.H(0, condition=exp)
+    exp2 = create_bit_logic_exp(BitWiseOp.ZERO, [])
+    circ.H(0, condition=exp2)
+
+    result = pytket_to_qir(
+        circ,
+        name="test_pytket_qir_conditional_12",
+        qir_format=QIRFormat.STRING,
+    )
+
+    check_qir_result(result, "test_pytket_qir_conditional_12")
+
+
 if __name__ == "__main__":
     test_pytket_qir_conditional()
     test_pytket_qir_conditional_ii()

diff --git a/tests/qir/test_pytket_qir_conditional_12.ll b/tests/qir/test_pytket_qir_conditional_12.ll
@@ -0,0 +1,72 @@
+; ModuleID = 'test_pytket_qir_conditional_12'
+source_filename = "test_pytket_qir_conditional_12"
+
+%Qubit = type opaque
+%Result = type opaque
+
+@0 = internal constant [15 x i8] c"tk_SCRATCH_BIT\00"
+
+define void @main() #0 {
+entry:
+  %0 = call i1* @create_creg(i64 2)
+  call void @set_creg_bit(i1* %0, i64 0, i1 true)
+  call void @set_creg_bit(i1* %0, i64 1, i1 false)
+  %1 = call i1 @get_creg_bit(i1* %0, i64 0)
+  br i1 %1, label %then, label %else
+
+then:                                             ; preds = %entry
+  call void @__quantum__qis__h__body(%Qubit* null)
+  br label %continue
+
+else:                                             ; preds = %entry
+  br label %continue
+
+continue:                                         ; preds = %else, %then
+  %2 = call i1 @get_creg_bit(i1* %0, i64 1)
+  br i1 %2, label %then1, label %else2
+
+then1:                                            ; preds = %continue
+  call void @__quantum__qis__h__body(%Qubit* null)
+  br label %continue3
+
+else2:                                            ; preds = %continue
+  br label %continue3
+
+continue3:                                        ; preds = %else2, %then1
+  call void @__quantum__rt__tuple_start_record_output()
+  %3 = call i64 @get_int_from_creg(i1* %0)
+  call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @0, i32 0, i32 0))
+  call void @__quantum__rt__tuple_end_record_output()
+  ret void
+}
+
+declare i1 @get_creg_bit(i1*, i64)
+
+declare void @set_creg_bit(i1*, i64, i1)
+
+declare void @set_creg_to_int(i1*, i64)
+
+declare i1 @__quantum__qis__read_result__body(%Result*)
+
+declare i1* @create_creg(i64)
+
+declare i64 @get_int_from_creg(i1*)
+
+declare void @mz_to_creg_bit(%Qubit*, i1*, i64)
+
+declare void @__quantum__rt__int_record_output(i64, i8*)
+
+declare void @__quantum__rt__tuple_start_record_output()
+
+declare void @__quantum__rt__tuple_end_record_output()
+
+declare void @__quantum__qis__h__body(%Qubit*)
+
+attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="7" "required_num_results"="7" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+
+!0 = !{i32 1, !"qir_major_version", i32 1}
+!1 = !{i32 7, !"qir_minor_version", i32 0}
+!2 = !{i32 1, !"dynamic_qubit_management", i1 false}
+!3 = !{i32 1, !"dynamic_result_management", i1 false}