Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

add trunc zext #166

Merged
merged 5 commits into from
Aug 22, 2024
Merged

add trunc zext #166

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
9b995ca
add zext and trunc
cqc-melf Aug 21, 2024
99373e2
regenerate qir files
cqc-melf Aug 21, 2024
e583b4b
update pyqir, version and changelog
cqc-melf Aug 21, 2024
b094f50
fix mypy
cqc-melf Aug 21, 2024
8bd2898
fix format
cqc-melf Aug 21, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion _metadata.py
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
__extension_version__ = "0.13.0rc0"
__extension_version__ = "0.13.0rc1"
__extension_name__ = "pytket-qir"
3 changes: 2 additions & 1 deletion docs/changelog.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,9 +1,10 @@
Changelog
~~~~~~~~~

0.13.0rc0 (August 2024)
0.13.0rc1 (August 2024)
-----------------------

* Updated pyqir version requirement to 0.10.4.
* Add option to generate profile compatible QIR

0.12.0 (July 2024)
Expand Down
24 changes: 17 additions & 7 deletions pytket/qir/conversion/pconversion.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,7 @@ def __init__(
self.active_block = None

self.cregs = _retrieve_registers(self.circuit.bits, BitRegister)
self.creg_size: dict[str, int] = {}
self.target_gateset = self.module.gateset.base_gateset

self.block_count = 0
Expand Down Expand Up @@ -250,6 +251,7 @@ def __init__(
for creg in self.circuit.c_registers:
self._reg2ssa_var(creg)
self.list_of_changed_cregs.append(creg)
self.creg_size[creg.name] = creg.size

def _get_bit_from_creg(self, creg: str, index: int) -> Value:
ssa_index = pyqir.const(self.qir_int_type, 2**index)
Expand Down Expand Up @@ -311,7 +313,7 @@ def _set_bit_in_creg(self, creg: str, index: int, ssa_bit: Value) -> None:
phi.add_incoming(result_0, sb_0)
phi.add_incoming(result_1, sb_1)

self.set_ssa_vars(creg, phi)
self.set_ssa_vars(creg, phi, False)

def get_ssa_vars(self, reg_name: str) -> Value:
if reg_name not in self.ssa_vars:
Expand All @@ -323,10 +325,18 @@ def get_ssa_list(self, reg_name: str) -> list:
raise ValueError(f"{reg_name} is not a valid register")
return self.ssa_vars[reg_name]

def set_ssa_vars(self, reg_name: str, i64value: Value) -> None:
def set_ssa_vars(self, reg_name: str, ssa_i64: Value, trunc: bool = True) -> None:
if reg_name not in self.ssa_vars:
raise ValueError(f"{reg_name} is not a valid register")
self.ssa_vars[reg_name].append((i64value, self.active_block)) # type: ignore
if trunc and self.creg_size[reg_name] != self.int_size:
type_register = pyqir.IntType(self.module.context, self.creg_size[reg_name])
ssa_i_trunc = self.module.module.builder.trunc(ssa_i64, type_register)
ssa_i64_zext = self.module.module.builder.zext(
ssa_i_trunc, self.qir_int_type
)
self.ssa_vars[reg_name].append((ssa_i64_zext, self.active_block)) # type: ignore
else:
self.ssa_vars[reg_name].append((ssa_i64, self.active_block)) # type: ignore
self.list_of_changed_cregs.append(reg_name)

def _add_barrier_op(
Expand Down Expand Up @@ -658,7 +668,7 @@ def conv_conditional(self, command: Command, op: Conditional) -> None:
"Second block missing after subcircuit_to_module conversion"
)

self.set_ssa_vars(creg, phi)
self.set_ssa_vars(creg, phi, False)

else:
for i in range(op.width):
Expand Down Expand Up @@ -722,7 +732,7 @@ def conv_conditional(self, command: Command, op: Conditional) -> None:
subcircuit_to_module conversion"
)

self.set_ssa_vars(creg, phi)
self.set_ssa_vars(creg, phi, False)

else:
condition_name = command.args[0].reg_name
Expand Down Expand Up @@ -773,7 +783,7 @@ def conv_conditional(self, command: Command, op: Conditional) -> None:
"Second block missing after command_to_module conversion"
)

self.set_ssa_vars(creg, phi)
self.set_ssa_vars(creg, phi, False)

else:
for i in range(op.width):
Expand Down Expand Up @@ -836,7 +846,7 @@ def conv_conditional(self, command: Command, op: Conditional) -> None:
command_to_module conversion"
)

self.set_ssa_vars(creg, phi)
self.set_ssa_vars(creg, phi, False)

def conv_WASMOp(self, op: WASMOp, args: Union[Bit, Qubit]) -> None:
paramreg, resultreg = self._get_c_regs_from_com(op, args)
Expand Down
2 changes: 1 addition & 1 deletion setup.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@
include_package_data=True,
install_requires=[
"pytket >= 1.31.0",
"pyqir >= 0.10.3",
"pyqir >= 0.10.4",
],
classifiers=[
"Environment :: Console",
Expand Down
Loading