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Remove hardware inefficient rz-sx decomposition for TK1 #1643

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Remove hardware inefficient rz-sx decomposition for TK1 #1643

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452f9b1
Update CircPool.cpp
sjdilkes Oct 30, 2024
60cccf6
bump
sjdilkes Oct 30, 2024
dc84f47
Update predicates_test.py
sjdilkes Oct 30, 2024
cdfef1c
Update changelog.rst
sjdilkes Oct 30, 2024
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2 changes: 1 addition & 1 deletion pytket/conanfile.py
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Expand Up @@ -38,7 +38,7 @@ def requirements(self):
self.requires("pybind11_json/0.2.14")
self.requires("symengine/0.12.0")
self.requires("tkassert/0.3.4@tket/stable")
self.requires("tket/1.3.36@tket/stable")
self.requires("tket/1.3.37@tket/stable")
self.requires("tklog/0.3.3@tket/stable")
self.requires("tkrng/0.3.3@tket/stable")
self.requires("tktokenswap/0.3.9@tket/stable")
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1 change: 1 addition & 0 deletions pytket/docs/changelog.rst
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Expand Up @@ -7,6 +7,7 @@ Unreleased
Fixes:

* Fix `symbol_substitution` not preserving opgroups.
* Remove hardware inefficient circuit construction in `_tk1_to_rzsx`

1.34.0 (October 2024)
---------------------
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9 changes: 9 additions & 0 deletions pytket/tests/predicates_test.py
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Expand Up @@ -846,6 +846,14 @@ def test_conditional_phase() -> None:
assert any(any_check_list)


def test_rz_sx_decomp() -> None:
c = Circuit(1).TK1(0, 1.5, 0, 0)
AutoRebase({OpType.CX, OpType.SX, OpType.Rz}).apply(c)
comp = Circuit(1).Rz(1, 0).SX(0).Rz(1, 0)
comp.add_phase(1.75)
assert c == comp


def test_flatten_relabel_pass() -> None:
c = Circuit(3)
c.H(1).H(2)
Expand Down Expand Up @@ -1112,3 +1120,4 @@ def test_auto_rebase_deprecation(recwarn: Any) -> None:
test_rebase_custom_tk2()
test_selectively_decompose_boxes()
test_clifford_push_through_measures()
test_rz_sx_decomp()
2 changes: 1 addition & 1 deletion tket/conanfile.py
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Expand Up @@ -23,7 +23,7 @@

class TketConan(ConanFile):
name = "tket"
version = "1.3.36"
version = "1.3.37"
package_type = "library"
license = "Apache 2"
homepage = "https://github.com/CQCL/tket"
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12 changes: 0 additions & 12 deletions tket/src/Circuit/CircPool.cpp
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Expand Up @@ -1306,18 +1306,6 @@ static Circuit _tk1_to_rzsx(
c.add_op<unsigned>(OpType::SX, {0});
c.add_op<unsigned>(OpType::Rz, alpha, {0});
correction_phase = int_half(beta - 0.5) - 0.25;
} else if (equiv_0(beta + 0.5) && equiv_0(alpha) && equiv_0(gamma)) {
// a = 2k, b = 2m-0.5, c = 2n
// Rz(2k)Rx(2m - 0.5)Rz(2n) = (-1)^{k+m+n}e^{i \pi /4} X.SX
if (allow_x) {
c.add_op<unsigned>(OpType::X, {0});
} else {
c.add_op<unsigned>(OpType::SX, {0});
c.add_op<unsigned>(OpType::SX, {0});
}
c.add_op<unsigned>(OpType::SX, {0});
correction_phase =
int_half(beta + 0.5) + int_half(alpha) + int_half(gamma) + 0.25;
} else if (equiv_0(beta + 0.5)) {
// SX.Rz(2m+0.5).SX = (-1)^{m}e^{i \pi /4} Rz(0.5).SX.Rz(0.5)
c.add_op<unsigned>(OpType::Rz, gamma + 1, {0});
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