CHERI-RISC-V: Use a bit in xCCSR to report we are tag clearing

This will allow detecting required CHERI features more easily and is
helpful for the transition period where older implementations still exist.

See also: CTSRD-CHERI/sail-cheri-riscv#74

target/riscv/cpu_bits.h

@@ -372,6 +372,7 @@
 #define XCCSR_DIRTY 0x2 /* Capability register written */
 #define SCCSR_SGCLG 0x4 /* Supervisor Global Cap Load Generation */
 #define SCCSR_UGCLG 0x8 /* User Global Cap Load Generation */
+#define XCCSR_TAG_CLEARING 0x80000000 /* CHERI has tag-clearing semantics. */
 #endif
 
 /* mstatus CSR bits */

target/riscv/csr.c

@@ -1341,6 +1341,8 @@ static int read_ccsr(CPURISCVState *env, int csrno, target_ulong *val)
  target_ulong ccsr = 0;
  ccsr = set_field(ccsr, XCCSR_ENABLE, cpu->cfg.ext_cheri);
  ccsr = set_field(ccsr, XCCSR_DIRTY, 1); /* Always report dirty */
+ /* Read-only feature bits. */
+ ccsr = set_field(ccsr, XCCSR_TAG_CLEARING, 1);
 
 #if !defined(TARGET_RISCV32)
  if (csrno == CSR_SCCSR)