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Merge tag 'drm-msm-next-2025-01-07' of gitlab.freedesktop.org:drm/msm…
… into drm-next Updates for v6.14 MDSS: - properly described UBWC registers - added SM6150 (aka QCS615) support MDP4: - several small fixes DPU: - added SM6150 (aka QCS615) support - enabled wide planes if virtual planes are enabled (by using two SSPPs for a single plane) - fixed modes filtering for platforms w/o 3DMux - fixed DSPP DSPP_2 / _3 links on several platforms - corrected DSPP definitions on SDM670 - added CWB hardware blocks support - added VBIF to DPU snapshots - dropped struct dpu_rm_requirements DP: - reworked DP audio support DSI: - added SM6150 (aka QCS615) support GPU: - Print GMU core fw version - GMU bandwidth voting for a740 and a750 - Expose uche trap base via uapi - UAPI error reporting Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsutUu4ff6OpXNXxqf1xaV0rV6oV23VXNRiF0_OEfe72Q@mail.gmail.com
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108 changes: 108 additions & 0 deletions
108
Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml
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| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: Qualcomm SM6150 Display DPU | ||
|
|
||
| maintainers: | ||
| - Abhinav Kumar <quic_abhinavk@quicinc.com> | ||
| - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | ||
|
|
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| $ref: /schemas/display/msm/dpu-common.yaml# | ||
|
|
||
| properties: | ||
| compatible: | ||
| const: qcom,sm6150-dpu | ||
|
|
||
| reg: | ||
| items: | ||
| - description: Address offset and size for mdp register set | ||
| - description: Address offset and size for vbif register set | ||
|
|
||
| reg-names: | ||
| items: | ||
| - const: mdp | ||
| - const: vbif | ||
|
|
||
| clocks: | ||
| items: | ||
| - description: Display ahb clock | ||
| - description: Display hf axi clock | ||
| - description: Display core clock | ||
| - description: Display vsync clock | ||
|
|
||
| clock-names: | ||
| items: | ||
| - const: iface | ||
| - const: bus | ||
| - const: core | ||
| - const: vsync | ||
|
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| unevaluatedProperties: false | ||
|
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| examples: | ||
| - | | ||
| #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| #include <dt-bindings/power/qcom,rpmhpd.h> | ||
| display-controller@ae01000 { | ||
| compatible = "qcom,sm6150-dpu"; | ||
| reg = <0x0ae01000 0x8f000>, | ||
| <0x0aeb0000 0x2008>; | ||
| reg-names = "mdp", "vbif"; | ||
| clocks = <&dispcc_mdss_ahb_clk>, | ||
| <&gcc_disp_hf_axi_clk>, | ||
| <&dispcc_mdss_mdp_clk>, | ||
| <&dispcc_mdss_vsync_clk>; | ||
| clock-names = "iface", "bus", "core", "vsync"; | ||
| assigned-clocks = <&dispcc_mdss_vsync_clk>; | ||
| assigned-clock-rates = <19200000>; | ||
| operating-points-v2 = <&mdp_opp_table>; | ||
| power-domains = <&rpmhpd RPMHPD_CX>; | ||
| interrupt-parent = <&mdss>; | ||
| interrupts = <0>; | ||
| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| port@0 { | ||
| reg = <0>; | ||
| dpu_intf0_out: endpoint { | ||
| }; | ||
| }; | ||
| port@1 { | ||
| reg = <1>; | ||
| dpu_intf1_out: endpoint { | ||
| remote-endpoint = <&mdss_dsi0_in>; | ||
| }; | ||
| }; | ||
| }; | ||
| mdp_opp_table: opp-table { | ||
| compatible = "operating-points-v2"; | ||
| opp-19200000 { | ||
| opp-hz = /bits/ 64 <19200000>; | ||
| required-opps = <&rpmhpd_opp_low_svs>; | ||
| }; | ||
| opp-25600000 { | ||
| opp-hz = /bits/ 64 <25600000>; | ||
| required-opps = <&rpmhpd_opp_svs>; | ||
| }; | ||
| opp-307200000 { | ||
| opp-hz = /bits/ 64 <307200000>; | ||
| required-opps = <&rpmhpd_opp_nom>; | ||
| }; | ||
| }; | ||
| }; | ||
| ... |
245 changes: 245 additions & 0 deletions
245
Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
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| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: Qualcomm SM6150 Display MDSS | ||
|
|
||
| maintainers: | ||
| - Abhinav Kumar <quic_abhinavk@quicinc.com> | ||
| - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | ||
|
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||
| description: | ||
| Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates | ||
| sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree | ||
| bindings of MDSS are mentioned for SM6150 target. | ||
|
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| $ref: /schemas/display/msm/mdss-common.yaml# | ||
|
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| properties: | ||
| compatible: | ||
| items: | ||
| - const: qcom,sm6150-mdss | ||
|
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||
| clocks: | ||
| items: | ||
| - description: Display AHB clock from gcc | ||
| - description: Display hf axi clock | ||
| - description: Display core clock | ||
|
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||
| clock-names: | ||
| items: | ||
| - const: iface | ||
| - const: bus | ||
| - const: core | ||
|
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| iommus: | ||
| maxItems: 1 | ||
|
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| interconnects: | ||
| maxItems: 2 | ||
|
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| interconnect-names: | ||
| maxItems: 2 | ||
|
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| patternProperties: | ||
| "^display-controller@[0-9a-f]+$": | ||
| type: object | ||
| additionalProperties: true | ||
| properties: | ||
| compatible: | ||
| const: qcom,sm6150-dpu | ||
|
|
||
| "^dsi@[0-9a-f]+$": | ||
| type: object | ||
| additionalProperties: true | ||
| properties: | ||
| compatible: | ||
| items: | ||
| - const: qcom,sm6150-dsi-ctrl | ||
| - const: qcom,mdss-dsi-ctrl | ||
|
|
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| "^phy@[0-9a-f]+$": | ||
| type: object | ||
| additionalProperties: true | ||
| properties: | ||
| compatible: | ||
| const: qcom,sm6150-dsi-phy-14nm | ||
|
|
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| unevaluatedProperties: false | ||
|
|
||
| examples: | ||
| - | | ||
| #include <dt-bindings/clock/qcom,rpmh.h> | ||
| #include <dt-bindings/interconnect/qcom,icc.h> | ||
| #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> | ||
| #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| #include <dt-bindings/power/qcom,rpmhpd.h> | ||
| display-subsystem@ae00000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "qcom,sm6150-mdss"; | ||
| reg = <0x0ae00000 0x1000>; | ||
| reg-names = "mdss"; | ||
| interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS | ||
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, | ||
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY | ||
| &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; | ||
| interconnect-names = "mdp0-mem", "cpu-cfg"; | ||
| power-domains = <&dispcc_mdss_gdsc>; | ||
| clocks = <&dispcc_mdss_ahb_clk>, | ||
| <&gcc_disp_hf_axi_clk>, | ||
| <&dispcc_mdss_mdp_clk>; | ||
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| iommus = <&apps_smmu 0x800 0x0>; | ||
| ranges; | ||
| display-controller@ae01000 { | ||
| compatible = "qcom,sm6150-dpu"; | ||
| reg = <0x0ae01000 0x8f000>, | ||
| <0x0aeb0000 0x2008>; | ||
| reg-names = "mdp", "vbif"; | ||
| clocks = <&dispcc_mdss_ahb_clk>, | ||
| <&gcc_disp_hf_axi_clk>, | ||
| <&dispcc_mdss_mdp_clk>, | ||
| <&dispcc_mdss_vsync_clk>; | ||
| clock-names = "iface", "bus", "core", "vsync"; | ||
| assigned-clocks = <&dispcc_mdss_vsync_clk>; | ||
| assigned-clock-rates = <19200000>; | ||
| operating-points-v2 = <&mdp_opp_table>; | ||
| power-domains = <&rpmhpd RPMHPD_CX>; | ||
| interrupt-parent = <&mdss>; | ||
| interrupts = <0>; | ||
| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| port@0 { | ||
| reg = <0>; | ||
| dpu_intf0_out: endpoint { | ||
| }; | ||
| }; | ||
| port@1 { | ||
| reg = <1>; | ||
| dpu_intf1_out: endpoint { | ||
| remote-endpoint = <&mdss_dsi0_in>; | ||
| }; | ||
| }; | ||
| }; | ||
| mdp_opp_table: opp-table { | ||
| compatible = "operating-points-v2"; | ||
| opp-19200000 { | ||
| opp-hz = /bits/ 64 <19200000>; | ||
| required-opps = <&rpmhpd_opp_low_svs>; | ||
| }; | ||
| opp-25600000 { | ||
| opp-hz = /bits/ 64 <25600000>; | ||
| required-opps = <&rpmhpd_opp_svs>; | ||
| }; | ||
| opp-307200000 { | ||
| opp-hz = /bits/ 64 <307200000>; | ||
| required-opps = <&rpmhpd_opp_nom>; | ||
| }; | ||
| }; | ||
| }; | ||
| dsi@ae94000 { | ||
| compatible = "qcom,sm6150-dsi-ctrl", | ||
| "qcom,mdss-dsi-ctrl"; | ||
| reg = <0x0ae94000 0x400>; | ||
| reg-names = "dsi_ctrl"; | ||
| interrupt-parent = <&mdss>; | ||
| interrupts = <4>; | ||
| clocks = <&dispcc_mdss_byte0_clk>, | ||
| <&dispcc_mdss_byte0_intf_clk>, | ||
| <&dispcc_mdss_pclk0_clk>, | ||
| <&dispcc_mdss_esc0_clk>, | ||
| <&dispcc_mdss_ahb_clk>, | ||
| <&gcc_disp_hf_axi_clk>; | ||
| clock-names = "byte", | ||
| "byte_intf", | ||
| "pixel", | ||
| "core", | ||
| "iface", | ||
| "bus"; | ||
| assigned-clocks = <&dispcc_mdss_byte0_clk_src>, | ||
| <&dispcc_mdss_pclk0_clk_src>; | ||
| assigned-clock-parents = <&mdss_dsi0_phy 0>, | ||
| <&mdss_dsi0_phy 1>; | ||
| operating-points-v2 = <&dsi0_opp_table>; | ||
| phys = <&mdss_dsi0_phy>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| port@0 { | ||
| reg = <0>; | ||
| mdss_dsi0_in: endpoint { | ||
| remote-endpoint = <&dpu_intf1_out>; | ||
| }; | ||
| }; | ||
| port@1 { | ||
| reg = <1>; | ||
| mdss_dsi0_out: endpoint { | ||
| }; | ||
| }; | ||
| }; | ||
| dsi0_opp_table: opp-table { | ||
| compatible = "operating-points-v2"; | ||
| opp-164000000 { | ||
| opp-hz = /bits/ 64 <164000000>; | ||
| required-opps = <&rpmhpd_opp_low_svs>; | ||
| }; | ||
| }; | ||
| }; | ||
| mdss_dsi0_phy: phy@ae94400 { | ||
| compatible = "qcom,sm6150-dsi-phy-14nm"; | ||
| reg = <0x0ae94400 0x100>, | ||
| <0x0ae94500 0x300>, | ||
| <0x0ae94800 0x188>; | ||
| reg-names = "dsi_phy", | ||
| "dsi_phy_lane", | ||
| "dsi_pll"; | ||
| #clock-cells = <1>; | ||
| #phy-cells = <0>; | ||
| clocks = <&dispcc_mdss_ahb_clk>, | ||
| <&rpmhcc RPMH_CXO_CLK>; | ||
| clock-names = "iface", "ref"; | ||
| }; | ||
| }; | ||
| ... |
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