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Use Amaranth SoC GPIO peripheral #20

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merged 2 commits into from
Jul 2, 2024
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@jfng jfng commented Jul 2, 2024

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jfng added 2 commits July 2, 2024 11:20
Otherwise, GCC/Clang will serialize 32-bit accesses as four 8-bit
instructions. Clang will schedule them in descending order, which
violates the SoC memory model (Amaranth SoC CSRs must be accessed
in ascending order of addresses).
@jfng jfng merged commit d92258e into ChipFlow:main Jul 2, 2024
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@jfng jfng deleted the amaranth-soc-gpio branch July 3, 2024 17:02
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