Table of Contents rendered at the bottom of the page fixed

_layouts/default.html

@@ -176,8 +176,8 @@
           </nav>
           {% endif %} {% endunless %}
           <div id="main-content" class="page-content" role="main">
-            {{ content }} {% if page.has_children == true and page.has_toc !=
-            false %}
+            {{ content }} {% if page.has_children == true and page.has_toc ==
+            true %}
             <hr />
             <h2 class="text-delta">Table of contents</h2>
             {% assign children_list = site.pages | sort:"nav_order" %}

docs/Combinational/N-Bit Parallel Adder & Subtractor.md

@@ -10,12 +10,21 @@ comments: true
 # N-Bit Parallel Adder
 {: .no_toc }
 
+## Table of contents
+{: .no_toc .text-delta }
+
+1. TOC
+{:toc}
+
+## Introduction
+
 The Full Adder is capable of adding only two single digit binary number along with a carry input. 
 But in practical we need to add binary numbers which are much longer than just one bit. To add two n-bit binary numbers we need to use the n-bit parallel adder. 
 It uses a number of full adders in cascade. 
 The carry output of the previous full adder is connected to carry input of the next full adder.
 
 ## 4 Bit Parallel Adder
+
 In the block diagram, A0 and B0 represent the LSB of the four bit words A and B. 
 Hence Full Adder-0 is the lowest stage. 
 Hence its Cin has been permanently made 0. 
@@ -25,16 +34,15 @@ The rest of the connections are exactly same as those of n-bit parallel adder is
 
 <div style="text-align:center"><img src="../../assets/images/fourbitadder_blockdiagram.jpg" /></div>
 
-
 # N-Bit Parallel Subtractor
-{: .no_toc }
 
 The subtraction can be carried out by taking the 1's or 2's complement of the number to be subtracted. 
 For example we can perform the subtraction (A-B) by adding either 1's or 2's complement of B to A. 
 That means we can use a binary adder to perform the binary subtraction.
 
 
 ## 4 Bit Parallel Subtractor
+
 The number to be subtracted (B) is first passed through inverters to obtain its 1's complement. 
 The 4-bit adder then adds A and 2's complement of B to produce the subtraction. 
 S3 S2 S1 S0 represents the result of binary subtraction (A-B) and carry output Cout represents the polarity of the result. 
@@ -46,7 +54,8 @@ If A > B then Cout = 0 and the result of binary form (A-B) then Cout = 1 and the
 <div style="text-align:center"><img src="../../assets/images/fourbitsubstractor_blockdiagram.jpg" /></div>
 
 
-## 8 Bit Full Adder And Subtractor   
+## 8 Bit Full Adder And Subtractor
+
 <iframe width="100%" height="400px" src="https://circuitverse.org/simulator/embed/2018" id="projectPreview" scrolling="no" webkitAllowFullScreen mozAllowFullScreen allowFullScreen> </iframe>
 
 {% include disqus.html %}

docs/Combinational/combinational.md

@@ -8,6 +8,15 @@ permalink: /docs/combinational
 # Digital Combinational Circuits
 {: .no_toc }
 
+## Table of Contents
+
+- [Half Adder](https://learn.circuitverse.org/docs/Combinational/half_adder.html)
+- [Full Adder](https://learn.circuitverse.org/docs/Combinational/full_adder.html)
+- [Half Subtractor](https://learn.circuitverse.org/docs/Combinational/half_sub.html)
+- [Full Subtractor](https://learn.circuitverse.org/docs/Combinational/full_sub.html)
+- [N-bit Parallel Adder and Subtractor](https://learn.circuitverse.org/docs/Combinational/N-Bit%20Parallel%20Adder%20&%20Subtractor.html)
+
+## Introduction
 
 Combinational circuits consist of Logic gates. These circuits operate with binary values. The output(s) of combinational circuit depends on the combination of present inputs. The following figure shows the **block diagram** of combinational circuit.
 

docs/Combinational/full_adder.md

@@ -9,25 +9,30 @@ comments: true
 # Full Adder
 {: .no_toc }
 
+## Table of contents
+{: .no_toc .text-delta }
+
+1. TOC
+{:toc}
+
+## Introduction
+
 Full adder is developed to overcome the drawback of Half Adder circuit. 
 It can add two one-bit numbers A and B, and carry c. 
 The full adder is a three input and two output combinational circuit.
 
 
 
 ## Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/fulladder_blockdiagram.jpg" /></div>
 
 
 ## Truth Table
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/fulladder_truthtable.jpg" /></div>
 
 ## Circuit Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/fulladder_circuitdiagram.jpg" /></div>
 

docs/Combinational/full_sub.md

@@ -9,17 +9,23 @@ comments: true
 # Full Subtractors
 {: .no_toc }
 
+## Table of contents
+{: .no_toc .text-delta }
+
+1. TOC
+{:toc}
+
+## Introduction
+
 The disadvantage of a half subtractor is overcome by full subtractor. 
 The full subtractor is a combinational circuit with three inputs A,B,C and two output D and C'. 
 A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output and C' is the borrow output.
 
 ## Truth Table
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/fullsubstrator_truthtable.jpg" /></div>
 
 ## Circuit Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/fullsubstrator_circuitdiagram.jpg" /></div>
 

docs/Combinational/half_adder.md

@@ -9,6 +9,14 @@ comments: true
 # Half Adder
 {: .no_toc }
 
+## Table of contents
+{: .no_toc .text-delta }
+
+1. TOC
+{:toc}
+
+## Introduction
+
 Half adder is a combinational logic circuit with two inputs and two outputs. 
 The half adder circuit is designed to add two single bit binary number A and B. 
 It is the basic building block for addition of two single bit numbers. 
@@ -17,18 +25,15 @@ This circuit has two outputs **carry** and **sum**.
 
 
 ## Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/halfadder_blockdiagram.jpg" /></div>
 
 
 ## Truth Table
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/halfadder_truthtable.jpg" /></div>
 
 ## Circuit Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/halfadder_circuitdiagram.jpg" /></div>
 

docs/Combinational/half_sub.md

@@ -9,17 +9,23 @@ comments: true
 # Half Subtractors
 {: .no_toc }
 
+## Table of contents
+{: .no_toc .text-delta }
+
+1. TOC
+{:toc}
+
+## Introduction
+
 Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). 
 It produces the difference between the two binary bits at the input and also produces an output (Borrow) to indicate if a 1 has been borrowed. 
 In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.
 
 ## Truth Table
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/halfsubstrator_truthtable.jpg" /></div>
 
 ## Circuit Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/halfsubstrator_circuitdiagram.jpg" /></div>
 

docs/MSI/decoder.md

@@ -9,34 +9,36 @@ comments: true
 # Multiplexers
 {: .no_toc }
 
+1. TOC
+{:toc}
+
+## Introduction
+
 A decoder is a combinational circuit. 
 It has n input and to a maximum m = 2n outputs. 
 Decoder is identical to a demultiplexer without any data input. 
 It performs operations which are exactly opposite to those of an encoder.
 
 
 ## Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/decoder_blockdiagram.jpg" /></div>
 
-### Examples of Decoders are following.
+### Examples of Decoders ::
 
 * Code converters
 * BCD to seven segment decoders
 * Nixie tube decoders
 * Relay actuator
 
 ## 2 to 4 Line Decoder
-{: .no_toc }
 
 The block diagram of 2 to 4 line decoder is shown in the fig. 
 A and B are the two inputs where D through D are the four outputs. 
 Truth table explains the operations of a decoder. 
 It shows that each output is 1 for only a specific combination of inputs.
 
 ## Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/two_fourdecoder_blockdiagram.jpg" /></div>
 

docs/MSI/demux.md

@@ -9,6 +9,11 @@ comments: true
 # Demultiplexers
 {: .no_toc }
 
+1. TOC
+{:toc}
+
+## Introduction
+
 A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. 
 It has only one input, n outputs, m select input. 
 At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. 
@@ -18,13 +23,11 @@ A de-multiplexer is equivalent to a single pole multiple way switch as shown in
 
 ### 1 : 2  demultiplexer
 #### Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/one_twodemultiplexer_blockdiagram.jpg" /></div>
 
 
 #### Truth Table
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/one_twodemultiplexer_truthtable.jpg" /></div>
 

docs/MSI/encoder.md

@@ -9,24 +9,27 @@ comments: true
 # Encoder
 {: .no_toc }
 
+1. TOC
+{:toc}
+
+## Introduction
+
 Encoder is a combinational circuit which is designed to perform the inverse operation of the decoder. 
 An encoder has n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to the digital input number. 
 The encoder accepts an n input digital word and converts it into an m bit another digital word.
 
 ## Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/encoder_blockdiagram.jpg" /></div>
 
-### Examples of Decoders are following.
+### Examples of Encoders ::
 
 * Priority encoders
 * Decimal to BCD encoder
 * Octal to binary encoder
 * Hexadecimal to binary encoder
 
 ## Priority Encoder
-{: .no_toc }
 
 This is a special type of encoder. 
 Priority is given to the input lines. 
@@ -36,7 +39,6 @@ Out of the four input D3 has the highest priority and D0 has the lowest priority
 That means if D3 = 1 then Y1 Y1 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the other inputs.
 
 ## Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/priorityencoder_blockdiagram.jpg" /></div>
 

docs/MSI/msi.md

@@ -8,6 +8,14 @@ permalink: /docs/msi
 # MSI
 {: .no_toc }
 
+## Table of Contents
+
+- [Multiplexers](https://learn.circuitverse.org/docs/MSI/mux.html)
+- [DeMultiplexers](https://learn.circuitverse.org/docs/MSI/demux.html)
+- [Decoder](https://learn.circuitverse.org/docs/MSI/decoder.html)
+- [Encoder](https://learn.circuitverse.org/docs/MSI/encoder.html)
+
+## Introduction
 
 Digital systems obtain binary-coded data and information that are continuously being operated on in some manner. 
 Some of the operations include:

docs/MSI/mux.md

@@ -9,6 +9,11 @@ comments: true
 # Multiplexers
 {: .no_toc }
 
+1. TOC
+{:toc}
+
+## Introduction
+
 Multiplexer is a special type of combinational circuit. 
 There are n-data inputs, one output and m select inputs with 2<sup>m</sup> = n. 
 It is a digital circuit which selects one of the n data inputs and routes it to the output. 
@@ -17,7 +22,6 @@ E is called the strobe or enable input which is useful for the cascading. It is
 
 
 ## Block Diagram
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/n_onemultiplexer_blockdiagram.jpg" /></div>
 
@@ -27,7 +31,6 @@ E is called the strobe or enable input which is useful for the cascading. It is
 
 ### 2 : 1 multiplexer
 #### Truth Table
-{: .no_toc }
 
 <div style="text-align:center"><img src="../../assets/images/two_onemultiplexer_truthtable.jpg" /></div>
 

docs/flipflop/d_flipflop.md

@@ -5,7 +5,15 @@ parent: Flip-Flops
 nav_order: 2
 comments: true
 ---
-## D Flip-Flop
+# D Flip-Flop
+
+## Table of contents
+{: .no_toc .text-delta }
+
+1. TOC
+{:toc}
+
+## Introduction
 
 D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, D latch operates with enable signal. That means, the output of D flip-flop is insensitive to the changes in the input, D except for active transition of the clock signal. The circuit diagram of D flip-flop is shown in the following figure.
 
@@ -14,7 +22,7 @@ D flip-flop operates with only positive clock transitions or negative clock tran
 This circuit has single input D and two outputs Q(t) & Q(t)’. The operation of D flip-flop is similar to D Latch. But, this flip-flop affects the outputs only when positive transition of the clock signal is applied instead of active enable.
 
 
-### State table of **D** flip-flop.
+## State table of **D** flip-flop.
 
 | D    |    Q(t+1) | 
 |:-------|:--------|

docs/flipflop/flipflops.md

@@ -9,6 +9,16 @@ permalink: /docs/flipflop
 # Flip-Flops
 {: .no_toc }
 
+## Table of Contents
+
+- [S-R Flip Flop](https://learn.circuitverse.org/docs/flipflop/sr_flipflop.html)
+- [D Flip-Flop](https://learn.circuitverse.org/docs/flipflop/d_flipflop.html)
+- [J-K Flip Flop](https://learn.circuitverse.org/docs/flipflop/jk_flipflop.html)
+- [T Flip Flop](https://learn.circuitverse.org/docs/flipflop/t_flipflop.html)
+- [Master Slave J-K Flip Flop](https://learn.circuitverse.org/docs/flipflop/masterslave_jk_flipflop.html)
+
+## Introduction
+
 In previous module, we discussed about Latches. Those are the basic building blocks of flip-flops. We can implement flip-flops in two methods.
 
 In first method, cascade two latches in such a way that the first latch is enabled for every positive clock pulse and second latch is enabled for every negative clock pulse. So that the combination of these two latches become a flip-flop.