A naive CPU implementation of 5-stage RISC-V pipeline, supporting basic functions of exception and interruption, page table, TLB and VGA output.
Course project of Computer Organization, 2021 Fall at THU.
Contributors: Co1lin, tz039e, ThonyPan
Copied from Tsinghua GitLab. Considering privacy issues, commit records are removed.
Report and demo will be uploaded soon.