Running Baremetal tests with Verilator 5.008 and CEP 4.5 fails

[jordankrim]

./simulator-chipyard.harness-CEPVerilatorRocketConfig ../../sims/cep_cosim/testSuites/bareMetalTests/aesMacro/riscv_wrapper.elf +loadmem=../../sims/cep_cosim/testSuites/bareMetalTests/aesMacro/riscv_wrapper.hex +loadmem_addr=80000000
simulator-chipyard.harness-CEPVerilatorRocketConfig: ../fesvr/elfloader.cc:37: std::map<std::__cxx11::basic_string, long unsigned int> load_elf(const char*, memif_t*, reg_t*, unsigned int): Assertion `(((*eh64).e_ident[0] == 0x7f && (*eh64).e_ident[1] == 'E' && (*eh64).e_ident[2] == 'L' && (*eh64).e_ident[3] == 'F') && (*eh64).e_ident[4] == 1) || (((*eh64).e_ident[0] == 0x7f && (*eh64).e_ident[1] == 'E' && (*eh64).e_ident[2] == 'L' && (*eh64).e_ident[3] == 'F') && (*eh64).e_ident[4] == 2)' failed.

I added printf statements to the elfloader.cc. I went to toolchains/riscv-tools/riscv-isa-sim/build and did a make. It appears that elfloader.o is changed, however, I have added 3 lines of prints above the failing line 37 reported (see above) but when I run the test again it still reports the failure as on line 37. So it looks like the elfloader.cc that I modified is not being used. I redid the:
make SUB_PROJECT=cep_verilator
Rebuilt all the baremetal test .elf files, but nothing seems to print and the line 37 is still being reported as the error, so how do I successfully compile and utilize a change elfloader.cc file
OR
Is there another getter way to debug why this is failing?

[jordankrim]

So no answer on this?

[bchetwynd]

Unfortunately, higher priority tasking has prevented any progress.

[jordankrim]

I realize you do not have time to work on this, however, I am still trying to debug this. I noticed that in the SimDRAM.cc module, the memory interface seems to have been completely revamped from v4.4 . The problem I am seeing is that the ELF file is not being loaded correctly when Verilator is used. In v4.5 SimDRAM.cc there is not use of the +loadmem_addr plusarg anymore and that was used on the invocation line for Verilator. It seems like for some reason with Verilator the SimDRAM.cc module is now pointing to the incorrect memory location and therefore the ELF file fails like I show in the original post. If you have any thoughts/suggestions on this or how to debug further, I would really appreciate it.

[jordankrim]

I have hacked up 3 files and it appears to work now. it appears the so called new "magic" memory manager (mm) doesn't work for Verilator and thus trying to do a load_elf in SimDRAM.cc fails, so I just put back the old mm from CEP v4.4 under pragmas either #ifndef VERILATOR or #ifdef VERILATOR. There may be a better way to fix this problem, but this works, and the BareMetal tests still work as expected with Xcelium.