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53 changes: 53 additions & 0 deletions
53
target/linux/airoha/patches-6.6/039-v6.14-net-airoha-Enforce-ETS-Qdisc-priomap.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,53 @@ | ||
| From b56e4d660a9688ff83f5cbdc6e3ea063352d0d79 Mon Sep 17 00:00:00 2001 | ||
| From: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Date: Sun, 12 Jan 2025 19:32:45 +0100 | ||
| Subject: [PATCH] net: airoha: Enforce ETS Qdisc priomap | ||
|
|
||
| EN7581 SoC supports fixed QoS band priority where WRR queues have lowest | ||
| priorities with respect to SP ones. | ||
| E.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn | ||
|
|
||
| Enforce ETS Qdisc priomap according to the hw capabilities. | ||
|
|
||
| Suggested-by: Davide Caratti <dcaratti@redhat.com> | ||
| Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Reviewed-by: Davide Caratti <dcaratti@redhat.com> | ||
| Link: https://patch.msgid.link/20250112-airoha_ets_priomap-v1-1-fb616de159ba@kernel.org | ||
| Signed-off-by: Jakub Kicinski <kuba@kernel.org> | ||
| --- | ||
| drivers/net/ethernet/mediatek/airoha_eth.c | 17 +++++++++++++++-- | ||
| 1 file changed, 15 insertions(+), 2 deletions(-) | ||
|
|
||
| --- a/drivers/net/ethernet/mediatek/airoha_eth.c | ||
| +++ b/drivers/net/ethernet/mediatek/airoha_eth.c | ||
| @@ -2786,7 +2786,7 @@ static int airoha_qdma_set_tx_ets_sched( | ||
| struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; | ||
| enum tx_sched_mode mode = TC_SCH_SP; | ||
| u16 w[AIROHA_NUM_QOS_QUEUES] = {}; | ||
| - int i, nstrict = 0; | ||
| + int i, nstrict = 0, nwrr, qidx; | ||
|
|
||
| if (p->bands > AIROHA_NUM_QOS_QUEUES) | ||
| return -EINVAL; | ||
| @@ -2800,7 +2800,20 @@ static int airoha_qdma_set_tx_ets_sched( | ||
| if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) | ||
| return -EINVAL; | ||
|
|
||
| - for (i = 0; i < p->bands - nstrict; i++) | ||
| + /* EN7581 SoC supports fixed QoS band priority where WRR queues have | ||
| + * lowest priorities with respect to SP ones. | ||
| + * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn | ||
| + */ | ||
| + nwrr = p->bands - nstrict; | ||
| + qidx = nstrict && nwrr ? nstrict : 0; | ||
| + for (i = 1; i <= p->bands; i++) { | ||
| + if (p->priomap[i % AIROHA_NUM_QOS_QUEUES] != qidx) | ||
| + return -EINVAL; | ||
| + | ||
| + qidx = i == nwrr ? 0 : qidx + 1; | ||
| + } | ||
| + | ||
| + for (i = 0; i < nwrr; i++) | ||
| w[i] = p->weights[nstrict + i]; | ||
|
|
||
| if (!nstrict) |
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58 changes: 58 additions & 0 deletions
58
...t/linux/airoha/patches-6.6/401-PCI-mediatek-gen3-Rely-on-clk_bulk_prepare_enable-in.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,58 @@ | ||
| From 0e7a622da17da0042294860cdb7a2fac091d25b1 Mon Sep 17 00:00:00 2001 | ||
| Message-ID: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org> | ||
| From: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Date: Wed, 8 Jan 2025 10:50:40 +0100 | ||
| Subject: [PATCH 1/6] PCI: mediatek-gen3: Rely on clk_bulk_prepare_enable() in | ||
| mtk_pcie_en7581_power_up() | ||
| MIME-Version: 1.0 | ||
| Content-Type: text/plain; charset=UTF-8 | ||
| Content-Transfer-Encoding: 8bit | ||
|
|
||
| Replace clk_bulk_prepare() and clk_bulk_enable() with | ||
| clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine. | ||
|
|
||
| Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-1-21ac939a3b9b@kernel.org | ||
| Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> | ||
| Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | ||
| Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | ||
| --- | ||
| drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++----------- | ||
| 1 file changed, 3 insertions(+), 11 deletions(-) | ||
|
|
||
| --- a/drivers/pci/controller/pcie-mediatek-gen3.c | ||
| +++ b/drivers/pci/controller/pcie-mediatek-gen3.c | ||
| @@ -907,12 +907,6 @@ static int mtk_pcie_en7581_power_up(stru | ||
| pm_runtime_enable(dev); | ||
| pm_runtime_get_sync(dev); | ||
|
|
||
| - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); | ||
| - if (err) { | ||
| - dev_err(dev, "failed to prepare clock\n"); | ||
| - goto err_clk_prepare; | ||
| - } | ||
| - | ||
| val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | | ||
| FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | | ||
| FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | | ||
| @@ -925,17 +919,15 @@ static int mtk_pcie_en7581_power_up(stru | ||
| FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); | ||
| writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); | ||
|
|
||
| - err = clk_bulk_enable(pcie->num_clks, pcie->clks); | ||
| + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); | ||
| if (err) { | ||
| dev_err(dev, "failed to prepare clock\n"); | ||
| - goto err_clk_enable; | ||
| + goto err_clk_prepare_enable; | ||
| } | ||
|
|
||
| return 0; | ||
|
|
||
| -err_clk_enable: | ||
| - clk_bulk_unprepare(pcie->num_clks, pcie->clks); | ||
| -err_clk_prepare: | ||
| +err_clk_prepare_enable: | ||
| pm_runtime_put_sync(dev); | ||
| pm_runtime_disable(dev); | ||
| reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); |
89 changes: 89 additions & 0 deletions
89
...t/linux/airoha/patches-6.6/402-PCI-mediatek-gen3-Move-reset-assert-callbacks-in-.po.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,89 @@ | ||
| From e4c7dfd953f7618f0ccb70d87c1629634f306fab Mon Sep 17 00:00:00 2001 | ||
| Message-ID: <e4c7dfd953f7618f0ccb70d87c1629634f306fab.1736960708.git.lorenzo@kernel.org> | ||
| In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org> | ||
| References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org> | ||
| From: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Date: Wed, 8 Jan 2025 10:50:41 +0100 | ||
| Subject: [PATCH 2/6] PCI: mediatek-gen3: Move reset/assert callbacks in | ||
| .power_up() | ||
| MIME-Version: 1.0 | ||
| Content-Type: text/plain; charset=UTF-8 | ||
| Content-Transfer-Encoding: 8bit | ||
|
|
||
| In order to make the code more readable, the reset_control_bulk_assert() | ||
| function for PHY reset lines is moved to make it pair with | ||
| reset_control_bulk_deassert() in mtk_pcie_power_up() and | ||
| mtk_pcie_en7581_power_up(). The same change is done for | ||
| reset_control_assert() used to assert MAC reset line. | ||
|
|
||
| Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to | ||
| complete PCIe reset on MediaTek controller. | ||
|
|
||
| Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-2-21ac939a3b9b@kernel.org | ||
| Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> | ||
| Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | ||
| Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | ||
| --- | ||
| drivers/pci/controller/pcie-mediatek-gen3.c | 28 +++++++++++++-------- | ||
| 1 file changed, 18 insertions(+), 10 deletions(-) | ||
|
|
||
| --- a/drivers/pci/controller/pcie-mediatek-gen3.c | ||
| +++ b/drivers/pci/controller/pcie-mediatek-gen3.c | ||
| @@ -120,6 +120,8 @@ | ||
|
|
||
| #define MAX_NUM_PHY_RESETS 3 | ||
|
|
||
| +#define PCIE_MTK_RESET_TIME_US 10 | ||
| + | ||
| /* Time in ms needed to complete PCIe reset on EN7581 SoC */ | ||
| #define PCIE_EN7581_RESET_TIME_MS 100 | ||
|
|
||
| @@ -875,9 +877,14 @@ static int mtk_pcie_en7581_power_up(stru | ||
| u32 val; | ||
|
|
||
| /* | ||
| - * Wait for the time needed to complete the bulk assert in | ||
| - * mtk_pcie_setup for EN7581 SoC. | ||
| + * The controller may have been left out of reset by the bootloader | ||
| + * so make sure that we get a clean start by asserting resets here. | ||
| */ | ||
| + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, | ||
| + pcie->phy_resets); | ||
| + reset_control_assert(pcie->mac_reset); | ||
| + | ||
| + /* Wait for the time needed to complete the reset lines assert. */ | ||
| mdelay(PCIE_EN7581_RESET_TIME_MS); | ||
|
|
||
| err = phy_init(pcie->phy); | ||
| @@ -944,6 +951,15 @@ static int mtk_pcie_power_up(struct mtk_ | ||
| struct device *dev = pcie->dev; | ||
| int err; | ||
|
|
||
| + /* | ||
| + * The controller may have been left out of reset by the bootloader | ||
| + * so make sure that we get a clean start by asserting resets here. | ||
| + */ | ||
| + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, | ||
| + pcie->phy_resets); | ||
| + reset_control_assert(pcie->mac_reset); | ||
| + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); | ||
| + | ||
| /* PHY power on and enable pipe clock */ | ||
| err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); | ||
| if (err) { | ||
| @@ -1016,14 +1032,6 @@ static int mtk_pcie_setup(struct mtk_gen | ||
| * counter since the bulk is shared. | ||
| */ | ||
| reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); | ||
| - /* | ||
| - * The controller may have been left out of reset by the bootloader | ||
| - * so make sure that we get a clean start by asserting resets here. | ||
| - */ | ||
| - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); | ||
| - | ||
| - reset_control_assert(pcie->mac_reset); | ||
| - usleep_range(10, 20); | ||
|
|
||
| /* Don't touch the hardware registers before power up */ | ||
| err = pcie->soc->power_up(pcie); |
38 changes: 38 additions & 0 deletions
38
...t/linux/airoha/patches-6.6/403-PCI-mediatek-gen3-Add-comment-about-initialization-o.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,38 @@ | ||
| From 0c9d2d2ef0d916b490a9222ed20ff4616fca876d Mon Sep 17 00:00:00 2001 | ||
| Message-ID: <0c9d2d2ef0d916b490a9222ed20ff4616fca876d.1736960708.git.lorenzo@kernel.org> | ||
| In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org> | ||
| References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org> | ||
| From: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Date: Wed, 8 Jan 2025 10:50:42 +0100 | ||
| Subject: [PATCH 3/6] PCI: mediatek-gen3: Add comment about initialization | ||
| order in mtk_pcie_en7581_power_up() | ||
| MIME-Version: 1.0 | ||
| Content-Type: text/plain; charset=UTF-8 | ||
| Content-Transfer-Encoding: 8bit | ||
|
|
||
| Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike the other | ||
| MediaTek Gen3 controllers, the Airoha EN7581 requires PHY initialization | ||
| and power-on before PHY reset deassert. | ||
|
|
||
| Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-3-21ac939a3b9b@kernel.org | ||
| Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> | ||
| Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> | ||
| Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | ||
| Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | ||
| --- | ||
| drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ | ||
| 1 file changed, 4 insertions(+) | ||
|
|
||
| --- a/drivers/pci/controller/pcie-mediatek-gen3.c | ||
| +++ b/drivers/pci/controller/pcie-mediatek-gen3.c | ||
| @@ -887,6 +887,10 @@ static int mtk_pcie_en7581_power_up(stru | ||
| /* Wait for the time needed to complete the reset lines assert. */ | ||
| mdelay(PCIE_EN7581_RESET_TIME_MS); | ||
|
|
||
| + /* | ||
| + * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 | ||
| + * requires PHY initialization and power-on before PHY reset deassert. | ||
| + */ | ||
| err = phy_init(pcie->phy); | ||
| if (err) { | ||
| dev_err(dev, "failed to initialize PHY\n"); |
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