Head of empty list error for if

[MartinC45]

Description

Same error message as #116 and seems related to if statements again. The error occurs for both VHDL and Verilog.

Example

import dfhdl.*

class DictControl(
    val fetch_count : Int <> CONST,  // set to 2
    val dict_entry_size : Int = 20
) extends RTDesign:
    val dict_in = Bits(fetch_count * dict_entry_size) <> IN 
    
    val matching = Bits(fetch_count) <> VAR
    val addr_r = Bits(12) <> VAR.REG init all(0)
    val idx_r = Bits(12) <> VAR.REG init all(0)
    val sym_r = Bits(8) <> VAR.REG init all(0)
    val entry_count = UInt(12) <> VAR.REG init 0
    
    entry_count.din := 0
    sym_r.din := b"8'0"
    idx_r.din := b"12'0"
    addr_r.din := b"12'0"
    
    for (i <- 0 until fetch_count.toScalaInt)
        if ((dict_in(dict_entry_size * (i+1) - 1, dict_entry_size * i) == (idx_r, sym_r)) && (addr_r + i < entry_count - 1))
            matching(i) := 1

@main def main = 
   DictControl(fetch_count = 2).compile

Output

Exception in thread "main" java.util.NoSuchElementException: head of empty list
        at scala.collection.immutable.Nil$.head(List.scala:662)
        at scala.collection.immutable.Nil$.head(List.scala:661)
        at dfhdl.compiler.ir.DB.OMLGen(DB.scala:137)
        at dfhdl.compiler.ir.DB.blockMemberList$lzyINIT1(DB.scala:221)
        at dfhdl.compiler.ir.DB.blockMemberList(DB.scala:221)
        at dfhdl.compiler.stages.UniqueNames.transform(UniqueNames.scala:72)
        at dfhdl.compiler.stages.StageRunner.runSingleStage(StageRunner.scala:22)
        at dfhdl.compiler.stages.StageRunner.dfhdl$compiler$stages$StageRunner$$run(StageRunner.scala:43)
        at dfhdl.compiler.stages.StageRunner$.run(StageRunner.scala:55)
        at dfhdl.backends$vhdl.printer(backends.scala:27)
        at dfhdl.compiler.stages.BackendCompiler.compile(BackendCompiler.scala:19)
        at dfhdl.compiler.stages.BackendCompiler.compile$(BackendCompiler.scala:8)
        at dfhdl.backends$vhdl.compile(backends.scala:23)
        at dfhdl.compiler.stages.StagedDesign$.compile(StagedDesign.scala:13)
        at dfhdl.ops$package$.compile(ops.scala:10)
        at project$package$.main(project.scala:39)
        at main.main(project.scala:27)

[soronpo]

Minimized:

import dfhdl.*
class DictControl(val fetch_count: Int <> CONST) extends RTDesign():
  val c        = Boolean           <> IN
  val matching = Bits(fetch_count) <> VAR
  if (c) matching(0) := 1

@main def main = DictControl(fetch_count = 2).compile