soc/power9/istep_8_11.c: enable RI/DI for XBus

Change-Id: I8e1f18080ecf11caea23890a826969394eaa658d
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>

src/include/cpu/power/istep_8.h

@@ -11,6 +11,7 @@ void istep_8_3(uint8_t chips);
 void istep_8_4(uint8_t chips);
 void istep_8_9(uint8_t chips);
 void istep_8_10(uint8_t chips);
+void istep_8_11(uint8_t chips);
 
 /* These functions access SCOM of the second CPU using SBE IO, thus they can be
  * used only in isteps that come after 8.4 */

src/soc/ibm/power9/Makefile.inc

@@ -15,6 +15,7 @@ romstage-y += istep_8_3.c
 romstage-y += istep_8_4.c
 romstage-y += istep_8_9.c
 romstage-y += istep_8_10.c
+romstage-y += istep_8_11.c
 romstage-y += istep_10_10.c
 romstage-y += istep_10_12.c
 romstage-y += istep_10_13.c

src/soc/ibm/power9/istep_8_11.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/power/istep_8.h>
+
+#include <console/console.h>
+#include <cpu/power/scom.h>
+
+static void xbus_enable_ridi(uint8_t chip)
+{
+	enum {
+		PERV_NET_CTRL0 = 0x060F0040,
+		PERV_NET_CTRL0_WOR = 0x060F0042,
+	};
+
+	/* Getting NET_CTRL0 register value and checking its CHIPLET_ENABLE bit */
+	if (get_scom(chip, PERV_NET_CTRL0) & PPC_BIT(0)) {
+		/* Enable Recievers, Drivers DI1 & DI2 */
+		uint64_t val = 0;
+		val |= PPC_BIT(19); // NET_CTRL0.RI_N = 1
+		val |= PPC_BIT(20); // NET_CTRL0.DI1_N = 1
+		val |= PPC_BIT(21); // NET_CTRL0.DI2_N = 1
+		put_scom(chip, PERV_NET_CTRL0_WOR, val);
+	}
+}
+
+void istep_8_11(uint8_t chips)
+{
+	printk(BIOS_EMERG, "starting istep 8.11\n");
+	report_istep(8,11);
+
+	if (chips != 0x01) {
+		xbus_enable_ridi(/*chip=*/0);
+		xbus_enable_ridi(/*chip=*/1);
+	}
+
+	printk(BIOS_EMERG, "ending istep 8.11\n");
+}

src/soc/ibm/power9/romstage.c

@@ -370,6 +370,7 @@ void main(void)
 	istep_8_4(chips);
 	istep_8_9(chips);
 	istep_8_10(chips);
+	istep_8_11(chips);
 
 	istep_10_10(&phb_active_mask, iovalid_enable);
 	istep_10_12();