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Apu2 iommu fix #592

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Apu2 iommu fix #592

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Commits on Nov 23, 2024

  1. northbridge/amd/pi/00730F01/acpi/northbridge.asl: Add IOMMU device 

    Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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    miczyg1 committed Nov 23, 2024
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  2. src/mainboard/pcengines/apu2/acpi/routing.asl: Add PCI INT routing fo… 

    …r IOMMU

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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  3. northbridge/amd/pi/00730F01/northbridge.c: Disable Guest AVIC 

    Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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  4. nb/amd/pi/00730F01/northbridge.c: Enable GNB IOAPIC in northbridge_init 

    Move the GNB IOAPIC enabling to northbridge init where the IOAPIC is
initialized.

Remove the comment about IoapicSbFeatureEn, this bit is not touched
here.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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  5. src/mainboard/pcengines/apu2/mainboard.c: Assign INTB# to IRQ17 

    Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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  6. src/mainboard/pcengines/apu2/mainboard.c: Clear the right bits in ECC… 

    … register

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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    miczyg1 committed Nov 23, 2024
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Commits on Nov 26, 2024

  1. src/northbridge/amd/pi/00730F01/northbridge.c: Add PCI_DEVID macro 

    Introduce PCI_DEVID macro which allows to construct PCI device
addresses or range with bus numbers.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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    miczyg1 committed Nov 26, 2024
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  2. src/northbridge/amd/pi/00730F01/northbridge.c: Rework IVRS generation 

    Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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    miczyg1 committed Nov 26, 2024
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  3. northbridge/amd/pi/00730F01/northbridge.c: Soft reserve CC6 save stat… 

    …e area

Use the IORESOURCE_SOFT_RESERVE attribute to reserve CC6 save state DRAM.
Using regualr reserved memory makes it hard on EDK2 to detect if it is MMIO
or reserved DRAM, as TOM2 is equal to the base of the CC6 save state area,
not its limit.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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  4. configs/config.pcengines_uefi_apu: Bump edk2 revision to fix IOMMU 

    Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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    miczyg1 committed Nov 26, 2024
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  5. nb/amd/pi/00730F01,dsdt_top: Add hook for _PIC method 

    Per family 16h models 30h-3fh BKDG the IoapicSbFeatureEn must be
configured according to the interrupt routing mode selecte by OS.
If OS chose APIC mode, the IoapicSbFeatureEn must be cleared.
Otherwise, it must be set, meaning PIC mode is used.

Add a hook to _PIC method to call SoC/northbridge specific code to
set/clear the bit to configure GNB IOAPIC properly.

ACPI specification says that _PIC method is optional and can be
called by OSPM to provide the interrupt routing mode information to
the firmware. However, if the method is not called, the firmware
must assume PIC mode is used. AGESA sets the IoapicSbFeatureEn
already to be compliant with ACPI. Previously, coreboot cleared the
bit unconditionally and left a comment to move that part to DSDT.
The hook allows to clear the IoapicSbFeatureEn bit if OS chooses APIC
mode for interrupt routing.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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    miczyg1 committed Nov 26, 2024
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