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i#2626 AArch64 encoder: Add support for fmov from GPR to FPR.
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This commit adds encoder/decoder support for fmov from GPRs to FPRs.

It does not add support for the variant to move a 64 bit GPR to the top
of a 128 bit register (FMOV <Vd>.D[1], <Xn>). I think for that variant,
we would need a way to express the top half of a 128 bit register.

Issue #2626

Change-Id: I9105b5ce5cc38a6b6cd33c8390a8822b091a44cf
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fhahn committed May 15, 2018
1 parent 6d02275 commit 4b848c7
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Showing 5 changed files with 53 additions and 0 deletions.
7 changes: 7 additions & 0 deletions core/arch/aarch64/codec.txt
Original file line number Diff line number Diff line change
Expand Up @@ -951,6 +951,13 @@ x101101011000000000101xxxxxxxxxx cls wx0 : wx5
1101101011000000000011xxxxxxxxxx rev x0 : x5

# Data Processing - Scalar Floating-Point and Advanced SIMD
# FMOV (general) GPR to FP reg
0001111011100111000000xxxxxxxxxx fmov h0 : w5 # Armv8.2
0001111000100111000000xxxxxxxxxx fmov s0 : w5
1001111011100111000000xxxxxxxxxx fmov h0 : x5 # Armv8.2
1001111001100111000000xxxxxxxxxx fmov d0 : x5

# Generated patterns
# FABD
0x101110110xxxxx000101xxxxxxxxxx fabd dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011101x1xxxxx110101xxxxxxxxxx fabd dq0 : dq5 dq16 fsz
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9 changes: 9 additions & 0 deletions core/arch/aarch64/instr_create.h
Original file line number Diff line number Diff line change
Expand Up @@ -575,6 +575,15 @@
#define INSTR_CREATE_sub_shimm(dc, rd, rn, rm_or_imm, sht, sha) \
INSTR_CREATE_sub_shift(dc, rd, rn, rm_or_imm, sht, sha)

/**
* Creates a FMOV instruction to move between GPRs and floating point registers.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Rd The output register.
* \param Rm The first input register.
*/
#define INSTR_CREATE_fmov_general(dc, Rd, Rn) \
instr_create_1dst_1src(dc, OP_fmov, Rd, Rn)

/**
* Creates a FABD vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
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6 changes: 6 additions & 0 deletions suite/tests/api/dis-a64.txt
Original file line number Diff line number Diff line change
Expand Up @@ -1561,6 +1561,12 @@ fd3fffff : str d31, [sp,#32760] : str %d31 -> +0x7ff8(%sp)[8byte]
fd481041 : ldr d1, [x2,#4128] : ldr +0x1020(%x2)[8byte] -> %d1
fd7fffff : ldr d31, [sp,#32760] : ldr +0x7ff8(%sp)[8byte] -> %d31

# FMOV (general) GPR to FP reg
1ee70220 : fmov h0, w17 : fmov %w17 -> %h0
1e27012a : fmov s10, w9 : fmov %w9 -> %s10
9ee701e5 : fmov h5, x15 : fmov %x15 -> %h5
9e67004b : fmov d11, x2 : fmov %x2 -> %d11

# FABD
6ede1762 : fabd v2.8h, v27.8h, v30.8h : fabd %q27 %q30 $0x01 -> %q2
2ede1762 : fabd v2.4h, v27.4h, v30.4h : fabd %d27 %d30 $0x01 -> %d2
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26 changes: 26 additions & 0 deletions suite/tests/api/ir_aarch64.c
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Expand Up @@ -281,6 +281,29 @@ test_ldar(void *dc)
test_instr_encoding(dc, OP_ldarh, instr);
}

static void
test_fmov_general(void *dc)
{
byte *pc;
instr_t *instr;

instr = INSTR_CREATE_fmov_general(dc, opnd_create_reg(DR_REG_H10),
opnd_create_reg(DR_REG_W9));
test_instr_encoding(dc, OP_fmov, instr);

instr = INSTR_CREATE_fmov_general(dc, opnd_create_reg(DR_REG_S14),
opnd_create_reg(DR_REG_W4));
test_instr_encoding(dc, OP_fmov, instr);

instr = INSTR_CREATE_fmov_general(dc, opnd_create_reg(DR_REG_H23),
opnd_create_reg(DR_REG_X8));
test_instr_encoding(dc, OP_fmov, instr);

instr = INSTR_CREATE_fmov_general(dc, opnd_create_reg(DR_REG_D6),
opnd_create_reg(DR_REG_X24));
test_instr_encoding(dc, OP_fmov, instr);
}

static void
test_neon_fp_arithmetic(void *dc)
{
Expand Down Expand Up @@ -1558,6 +1581,9 @@ main(int argc, char *argv[])
test_ldar(dcontext);
print("test_ldar complete\n");

test_fmov_general(dcontext);
print("test_fmov_general complete\n");

test_neon_fp_arithmetic(dcontext);
print("test_neon_fp_arithmetic complete\n");

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5 changes: 5 additions & 0 deletions suite/tests/api/ir_aarch64.expect
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,11 @@ ldar (%x1)[8byte] -> %x0
ldarb (%x1)[1byte] -> %w0
ldarh (%x1)[2byte] -> %w0
test_ldar complete
fmov %w9 -> %h10
fmov %w4 -> %s14
fmov %x8 -> %h23
fmov %x24 -> %d6
test_fmov_general complete
fabd %q27 %q30 $0x01 -> %q2
fabd %d27 %d30 $0x01 -> %d2
fabd %q13 %q29 $0x02 -> %q0
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