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i#4059 faster Appveyor: No rel-32; shrink drcacheoff tests
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Removes the 32-bit release build from PR builds (the 64-bit should
catch nearly all warnings).

Further shrinks drcachesim tests using the Jacobi app by dropping to a
64 matrix size and 3 instead of 5 iterations.

Shrinks drcacheoff tests on Windows by capping the trace sizes at 1M,
except for basic_counts which needs the full run to see kernel events.
Relaxes all of the templates to allow for correspondingly varying
simulator statistics.

Issue: #4059
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@derekbruening
derekbruening committed Feb 22, 2020
1 parent 5557f35 commit c1436b0
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Showing 29 changed files with 221 additions and 249 deletions.
4 changes: 2 additions & 2 deletions clients/drcachesim/tests/TLB-simple.templatex
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Expand Up @@ -6,7 +6,7 @@ Core #0 \(1 thread\(s\)\)
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
Miss rate: 0[,\.]..%
Miss rate: [0-3][,\.]..%
L1D stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Expand All @@ -16,7 +16,7 @@ Core #0 \(1 thread\(s\)\)
Hits: *[0-9,\.]*
Misses: *[0-9]..?
Invalidations: *0
Local miss rate: *[0-9]*[,\.]..%
Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: 0[,\.]..%
Core #1 \(0 thread\(s\)\)
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16 changes: 3 additions & 13 deletions clients/drcachesim/tests/TLB-threads.templatex
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Expand Up @@ -5,7 +5,7 @@
Client version .*
...................................................................

Matrix Size : 128
Matrix Size : 64
Threads : 4


Expand All @@ -24,19 +24,9 @@
Finished computing current solution distance in mode 0.
Mode changed to 0.

Started iteration 4 of the computation...

Finished computing current solution distance in mode 0.
Mode changed to 0.

Started iteration 5 of the computation...

Finished computing current solution distance in mode 0.
Mode changed to 0.


The Jacobi Method For AX=B .........DONE
Total Number Of iterations : 5
Total Number Of iterations : 3
...................................................................
---- <application exited with code 0> ----
TLB simulation results:
Expand All @@ -55,7 +45,7 @@ Core #0 \([0-9] traced CPU\(s\): [#0-9, ]+\)
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *[0-9]*
Local miss rate: *[0-9]*[\.,]..%
Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: *[0-9,\.]*%
Core #1 \([0-9] traced CPU\(s\).*
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22 changes: 6 additions & 16 deletions clients/drcachesim/tests/coherence.templatex
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Expand Up @@ -5,7 +5,7 @@
Client version .*
...................................................................

Matrix Size : 128
Matrix Size : 64
Threads : 4


Expand All @@ -24,19 +24,9 @@
Finished computing current solution distance in mode 0.
Mode changed to 0.

Started iteration 4 of the computation...

Finished computing current solution distance in mode 0.
Mode changed to 0.

Started iteration 5 of the computation...

Finished computing current solution distance in mode 0.
Mode changed to 0.


The Jacobi Method For AX=B .........DONE
Total Number Of iterations : 5
Total Number Of iterations : 3
...................................................................
---- <application exited with code 0> ----
Cache simulation results:
Expand All @@ -57,11 +47,11 @@ Core #1 \(.*\).*
Core #2 \(.*\).*
Core #3 \(.*\).*
LL stats:
Hits: *[0-9,\.]*...
Misses: *[0-9,\.]*...
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[0-9]*[\.,]..%
Child hits: *[0-9,\.]*......
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: 0[\.,]..%
Coherence stats:
Total writes: *[0-9,\.]*
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12 changes: 6 additions & 6 deletions clients/drcachesim/tests/delay-simple.templatex
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Expand Up @@ -5,21 +5,21 @@ Cache simulation results:
Core #0 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: *[0-9,\.]*%
L1D stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: *[0-9,\.]*%
Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[0-9,\.]*%
Child hits: *[0-9,\.]*.
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: *[0-9,\.]*%
10 changes: 5 additions & 5 deletions clients/drcachesim/tests/filter-no-d.templatex
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Expand Up @@ -4,7 +4,7 @@ Cache simulation results:
Core #0 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: *[1-9][0-9][,\.]..%
L1D stats:
Expand All @@ -15,9 +15,9 @@ Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[1-9][0-9][,\.]..%
Child hits: *[0-9,\.]*.
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: *[1-9][0-9][,\.]..%
10 changes: 5 additions & 5 deletions clients/drcachesim/tests/filter-no-i.templatex
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Expand Up @@ -8,16 +8,16 @@ Core #0 \(1 thread\(s\)\)
Invalidations: 0
L1D stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: *[1-9][0-9][,\.]..%
Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[1-9][0-9][,\.]..%
Child hits: *[0-9,\.]*.
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: *[1-9][0-9][,\.]..%
12 changes: 6 additions & 6 deletions clients/drcachesim/tests/filter-simple.templatex
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Expand Up @@ -4,21 +4,21 @@ Cache simulation results:
Core #0 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: *[1-9][0-9][,\.]..%
L1D stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: *[1-9][0-9][,\.]..%
Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[1-9][0-9][,\.]..%
Child hits: *[0-9,\.]*.
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: *[1-9][0-9][,\.]..%
38 changes: 19 additions & 19 deletions clients/drcachesim/tests/missfile-config-file.templatex
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Expand Up @@ -3,26 +3,26 @@ Hello, world!
Cache simulation results:
Core #0 \([0-9] traced CPU\(s\): #.*\)
L1I stats:
Warmup hits: *[0-9,\.]*....
Warmup misses: *[0-9,\.]*..
Hits: *[0-9,\.]*....
Misses: *[0-9,\.]*..
Invalidations: *[0-9,\.]*..
Warmup hits: *[0-9,\.]*
Warmup misses: *[0-9,\.]*
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *[0-9,\.]*
.*L1D stats:
Warmup hits: *[0-9,\.]*....
Warmup misses: *[0-9,\.]*..
Hits: *[0-9,\.]*....
Misses: *[0-9,\.]*..
Invalidations: *[0-9,\.]*..
Warmup hits: *[0-9,\.]*
Warmup misses: *[0-9,\.]*
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *[0-9,\.]*
.*L2 stats:
Warmup hits: *[0-9,\.]*....
Warmup misses: *[0-9,\.]*..
Hits: *[0-9,\.]*....
Misses: *[0-9,\.]*...
Invalidations: *[0-9,\.]*..
Warmup hits: *[0-9,\.]*
Warmup misses: *[0-9,\.]*
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *[0-9,\.]*
.*LLC stats:
Warmup hits: *[0-9,\.]*....
Warmup misses: *[0-9,\.]*..
Hits: *[0-9,\.]*....
Misses: *[0-9,\.]*...
Warmup hits: *[0-9,\.]*
Warmup misses: *[0-9,\.]*
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0.*
8 changes: 4 additions & 4 deletions clients/drcachesim/tests/multiproc.templatex
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Expand Up @@ -6,18 +6,18 @@ Core #0 \(1 thread\(s\)\)
Hits: *[0-9]*[,\.]?...[,\.]?...
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
L1D stats:
Hits: *[0-9]*[,\.]?...[,\.]?...
Misses: *[0-9\.,]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
Core #1 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9]*[,\.]?...[,\.]?...
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
L1D stats:
Hits: *[0-9]*[,\.]?...[,\.]?...
Misses: *[0-9]*[,\.]?...
Expand All @@ -29,6 +29,6 @@ LL stats:
Hits: *[0-9]*
Misses: *[0-9]*[,\.]?...
Invalidations: *0
.* Local miss rate: *[1-9][0-9][,\.]..%
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*[,\.]?...[,\.]?...
Total miss rate: [0-9][,\.]..%
20 changes: 10 additions & 10 deletions clients/drcachesim/tests/offline-burst_client.templatex
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Expand Up @@ -25,22 +25,22 @@ all done
Cache simulation results:
Core #0 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9,\.]*.....
Misses: *[0-9,\.]*...
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
L1D stats:
Hits: *[0-9,\.]*.....
Misses: *[0-9,\.]*.
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[0-9]*[,\.]..%
Child hits: *[0-9,\.]*...
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: [0-1][,\.]..%
20 changes: 10 additions & 10 deletions clients/drcachesim/tests/offline-burst_maps.templatex
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Expand Up @@ -13,22 +13,22 @@ all done
Cache simulation results:
Core #0 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9,\.]*.....
Misses: *[0-9,\.]*...
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
L1D stats:
Hits: *[0-9,\.]*.....
Misses: *[0-9,\.]*.
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[0-9]*[,\.]..%
Child hits: *[0-9,\.]*...
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: [0-1][,\.]..%
20 changes: 10 additions & 10 deletions clients/drcachesim/tests/offline-burst_noreach.templatex
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Original file line number Diff line number Diff line change
Expand Up @@ -13,22 +13,22 @@ all done
Cache simulation results:
Core #0 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9,\.]*.....
Misses: *[0-9,\.]*...
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
L1D stats:
Hits: *[0-9,\.]*.....
Misses: *[0-9,\.]*.
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Miss rate: 0[,\.]..%
.* Miss rate: [0-3][,\.]..%
Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*
Invalidations: *0
.* Local miss rate: *[0-9]*[,\.]..%
Child hits: *[0-9,\.]*...
.* Local miss rate: *[0-9,.]*%
Child hits: *[0-9,\.]*
Total miss rate: [0-1][,\.]..%
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