i#1569 AArch64: Implement flush_icache in suite/tests/tools.[ch].

Move cache_sync_asm from aarch64.asm to aarch64_shared.asm and implement flush_icache with a branch to cache_sync_asm. This makes the tests TestAllocWE and TestMemProtChg work when run natively. Review-URL: https://codereview.appspot.com/310690043
DynamoRIO · Nov 15, 2016 · c6a93e1 · c6a93e1
1 parent 2943c05
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diff --git a/core/arch/aarch64/aarch64.asm b/core/arch/aarch64/aarch64.asm
@@ -556,42 +556,6 @@ GLOBAL_LABEL(back_from_native:)
         bl       GLOBAL_REF(unexpected_return) /* FIXME i#1569: NYI */
         END_FUNC(back_from_native)
 
-/* CTR_EL0 [19:16] : Log2 of number of words in smallest dcache line
- * CTR_EL0 [3:0]   : Log2 of number of words in smallest icache line
- *
- * PoC = Point of Coherency
- * PoU = Point of Unification
- *
- * void cache_sync_asm(void *beg, void *end);
- */
-        DECLARE_FUNC(cache_sync_asm)
-GLOBAL_LABEL(cache_sync_asm:)
-        mrs      x3, ctr_el0
-        mov      w4, #4
-        ubfx     w2, w3, #16, #4
-        lsl      w2, w4, w2 /* bytes in dcache line */
-        and      w3, w3, #15
-        lsl      w3, w4, w3 /* bytes in icache line */
-        sub      w4, w2, #1
-        bic      x4, x0, x4 /* aligned beg */
-        b        2f
-1:      dc       cvau, x4 /* Data Cache Clean by VA to PoU */
-        add      x4, x4, x2
-2:      cmp      x4, x1
-        b.cc     1b
-        dsb      ish /* Data Synchronization Barrier, Inner Shareable */
-        sub      w4, w3, #1
-        bic      x4, x0, x4 /* aligned beg */
-        b        4f
-3:      ic       ivau, x4 /* Instruction Cache Invalidate by VA to PoU */
-        add      x4, x4, x3
-4:      cmp      x4, x1
-        b.cc     3b
-        dsb      ish /* Data Synchronization Barrier, Inner Shareable */
-        isb      /* Instruction Synchronization Barrier */
-        ret
-        END_FUNC(cache_sync_asm)
-
 /* A static resolver for TLS descriptors, implemented in assembler as
  * it does not use the standard calling convention. In C, it could be:
  *

diff --git a/core/arch/aarch64/aarch64_shared.asm b/core/arch/aarch64/aarch64_shared.asm
@@ -73,4 +73,44 @@ GLOBAL_LABEL(FUNCNAME:)
         END_FUNC(FUNCNAME)
 #undef FUNCNAME
 
+/* CTR_EL0 [19:16] : Log2 of number of words in smallest dcache line
+ * CTR_EL0 [3:0]   : Log2 of number of words in smallest icache line
+ *
+ * PoC = Point of Coherency
+ * PoU = Point of Unification
+ *
+ * void cache_sync_asm(void *beg, void *end);
+ *
+ * FIXME i#1569: The values read from CTR_EL0 should be cached as
+ * MRS Xt, CTR_EL0 may be emulated by kernel. This function could
+ * be implemented in C with inline assembly.
+ */
+        DECLARE_FUNC(cache_sync_asm)
+GLOBAL_LABEL(cache_sync_asm:)
+        mrs      x3, ctr_el0
+        mov      w4, #4
+        ubfx     w2, w3, #16, #4
+        lsl      w2, w4, w2 /* bytes in dcache line */
+        and      w3, w3, #15
+        lsl      w3, w4, w3 /* bytes in icache line */
+        sub      w4, w2, #1
+        bic      x4, x0, x4 /* aligned beg */
+        b        2f
+1:      dc       cvau, x4 /* Data Cache Clean by VA to PoU */
+        add      x4, x4, x2
+2:      cmp      x4, x1
+        b.cc     1b
+        dsb      ish /* Data Synchronization Barrier, Inner Shareable */
+        sub      w4, w3, #1
+        bic      x4, x0, x4 /* aligned beg */
+        b        4f
+3:      ic       ivau, x4 /* Instruction Cache Invalidate by VA to PoU */
+        add      x4, x4, x3
+4:      cmp      x4, x1
+        b.cc     3b
+        dsb      ish /* Data Synchronization Barrier, Inner Shareable */
+        isb      /* Instruction Synchronization Barrier */
+        ret
+        END_FUNC(cache_sync_asm)
+
 END_FILE
diff --git a/core/lib/dr_helper.h b/core/lib/dr_helper.h
@@ -58,6 +58,10 @@ ptr_int_t dynamorio_syscall(uint sysnum, uint num_args, ...);
 # endif
 #endif
 
+#ifdef AARCH64
+void cache_sync_asm(void *beg, void *end);
+#endif
+
 void dr_fpu_exception_init(void);
 
 #ifdef X86

diff --git a/suite/tests/tools.c b/suite/tests/tools.c
@@ -663,21 +663,25 @@ GLOBAL_LABEL(FUNCNAME:)
 #endif
         END_FUNC(FUNCNAME)
 
-#ifdef ARM
+#ifdef AARCHXX
     /* gcc's __clear_cache is not easily usable: no header, need lib; so we just
      * roll our own.
      */
 # undef FUNCNAME
 # define FUNCNAME flush_icache
         DECLARE_FUNC(FUNCNAME)
 GLOBAL_LABEL(FUNCNAME:)
+# ifndef X64
         push     {r7}
         mov      r2, #0       /* flags: must be 0 */
         movw     r7, #0x0002  /* SYS_cacheflush bottom half */
         movt     r7, #0x000f  /* SYS_cacheflush top half */
         svc      #0           /* flush icache */
         pop      {r7}
         bx       lr
+# else
+        b        cache_sync_asm
+# endif
         END_FUNC(FUNCNAME)
 #endif
 

diff --git a/suite/tests/tools.h b/suite/tests/tools.h
@@ -324,7 +324,7 @@ int code_self_mod(int iters);
 int code_inc(int foo);
 int code_dec(int foo);
 int dummy(void);
-#ifdef ARM
+#ifdef AARCHXX
 void flush_icache(byte *start, byte *end);
 #endif
 
@@ -450,7 +450,7 @@ copy_to_buf_normal(char *buf, size_t buf_len, size_t *copied_len, Code_Snippet f
         len = buf_len;
     }
     memcpy(buf, start, len);
-#if defined(LINUX) && defined(ARM)
+#if defined(LINUX) && defined(AARCHXX)
     flush_icache((byte *)buf, (byte *)buf + len);
 #endif
     if (copied_len != NULL)