i#1569 AArch64: Replace "AARCH64 || ARM" with AARCHXX in many places.

Review-URL: https://codereview.appspot.com/302060043
DynamoRIO · Jun 28, 2016 · e74114f · e74114f
1 parent 0aceb3a
commit e74114f
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Showing 34 changed files with 104 additions and 104 deletions.
diff --git a/core/arch/arch.c b/core/arch/arch.c
@@ -427,7 +427,7 @@ shared_gencode_emit(generated_code_t *gencode _IF_X86_64(bool x86_mode))
     gencode->do_syscall = pc;
     pc = emit_do_syscall(GLOBAL_DCONTEXT, gencode, pc, gencode->fcache_return,
                          true/*shared*/, 0, &gencode->do_syscall_offs);
-# if defined(ARM) || defined(AARCH64)
+# ifdef AARCHXX
     /* ARM has no thread-private gencode, so our clone syscall is shared */
     gencode->do_clone_syscall = pc;
     pc = emit_do_clone_syscall(GLOBAL_DCONTEXT, gencode, pc, gencode->fcache_return,
@@ -569,7 +569,7 @@ shared_gencode_init(IF_X86_64_ELSE(gencode_mode_t gencode_mode, void))
     protect_generated_code(gencode, READONLY);
 }
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 /* Called during a reset when all threads are suspended */
 void
 arch_reset_stolen_reg(void)
@@ -680,7 +680,7 @@ arch_init(void)
     ASSERT(syscall_method != SYSCALL_METHOD_UNINITIALIZED);
 #endif
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
     dr_reg_stolen = DR_REG_R0 + DYNAMO_OPTION(steal_reg);
     ASSERT(dr_reg_stolen >= DR_REG_STOLEN_MIN && dr_reg_stolen <= DR_REG_STOLEN_MAX)
 #endif
@@ -1120,7 +1120,7 @@ arch_thread_init(dcontext_t *dcontext)
     return;
 #endif
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
     /* Store addresses we access via TLS from exit stubs and gencode. */
     get_local_state_extended()->spill_space.fcache_return =
         PC_AS_JMP_TGT(isa_mode, fcache_return_shared_routine());
@@ -2893,7 +2893,7 @@ hook_vsyscall(dcontext_t *dcontext)
     instr_free(dcontext, &instr);
     return res;
 # undef CHECK
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     /* No vsyscall support needed for our ARM targets */
     ASSERT_NOT_REACHED();
     return false;
@@ -2926,7 +2926,7 @@ unhook_vsyscall(void)
         ASSERT(res);
     }
     return true;
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     ASSERT_NOT_IMPLEMENTED(get_syscall_method() != SYSCALL_METHOD_SYSENTER);
     return false;
 #endif /* X86/ARM */
@@ -2948,7 +2948,7 @@ check_syscall_method(dcontext_t *dcontext, instr_t *instr)
     else if (instr_get_opcode(instr) == OP_call_ind)
         new_method = SYSCALL_METHOD_WOW64;
 # endif
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     if (instr_get_opcode(instr) == OP_svc)
         new_method = SYSCALL_METHOD_SVC;
 #endif /* X86/ARM */
@@ -3318,7 +3318,7 @@ dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml)
                , context->r8,  context->r9,  context->r10,  context->r11,
                context->r12, context->r13, context->r14,  context->r15
 # endif /* X64 */
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
                context->r0,  context->r1,  context->r2,  context->r3,
                context->r4,  context->r5,  context->r6,  context->r7,
                context->r8,  context->r9,  context->r10, context->r11,
@@ -3380,7 +3380,7 @@ dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml)
                context->xflags, context->pc);
 }
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 reg_t
 get_stolen_reg_val(priv_mcontext_t *mc)
 {

diff --git a/core/arch/arch.h b/core/arch/arch.h
@@ -114,7 +114,7 @@ mixed_mode_enabled(void)
 # define SCRATCH_REG3_OFFS XDX_OFFSET
 # define SCRATCH_REG4_OFFS XSI_OFFSET
 # define SCRATCH_REG5_OFFS XDI_OFFSET
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 # define R0_OFFSET         ((MC_OFFS) + (offsetof(priv_mcontext_t, r0)))
 # define R1_OFFSET         ((MC_OFFS) + (offsetof(priv_mcontext_t, r1)))
 # define R2_OFFSET         ((MC_OFFS) + (offsetof(priv_mcontext_t, r2)))
@@ -491,7 +491,7 @@ instr_t *
 mangle_rel_addr(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
                 instr_t *next_instr);
 #endif
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 /* mangle instructions that use pc or dr_reg_stolen */
 instr_t *
 mangle_special_registers(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
@@ -1317,7 +1317,7 @@ add_patch_entry_internal(patch_list_t *patch, instr_t *instr, ushort patch_flags
 cache_pc
 get_direct_exit_target(dcontext_t *dcontext, uint flags);
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 size_t
 get_fcache_return_tls_offs(dcontext_t *dcontext, uint flags);
 

diff --git a/core/arch/arch_exports.h b/core/arch/arch_exports.h
@@ -125,7 +125,7 @@ typedef struct _table_stat_state_t {
 #endif
 } table_stat_state_t;
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 typedef struct _ibl_entry_pc_t {
     byte *ibl;
     byte *unlinked;
@@ -140,13 +140,13 @@ typedef struct _spill_state_t {
     /* Four registers are used in the indirect branch lookup routines */
 #ifdef X86
     reg_t xax, xbx, xcx, xdx;    /* general-purpose registers */
-#elif defined (ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     reg_t r0, r1, r2, r3;
     reg_t reg_stolen;            /* slot for the stolen register */
 #endif
     /* FIXME: move this below the tables to fit more on cache line */
     dcontext_t *dcontext;
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
     /* We store addresses here so we can load pointer-sized addresses into
      * registers with a single instruction in our exit stubs and gencode.
      */
@@ -184,7 +184,7 @@ typedef struct _local_state_extended_t {
 # define SCRATCH_REG1             DR_REG_XBX
 # define SCRATCH_REG2             DR_REG_XCX
 # define SCRATCH_REG3             DR_REG_XDX
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 # define TLS_REG0_SLOT            ((ushort)offsetof(spill_state_t, r0))
 # define TLS_REG1_SLOT            ((ushort)offsetof(spill_state_t, r1))
 # define TLS_REG2_SLOT            ((ushort)offsetof(spill_state_t, r2))
@@ -198,7 +198,7 @@ typedef struct _local_state_extended_t {
 #define IBL_TARGET_REG           SCRATCH_REG2
 #define IBL_TARGET_SLOT          TLS_REG2_SLOT
 #define TLS_DCONTEXT_SLOT        ((ushort)offsetof(spill_state_t, dcontext))
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 # define TLS_FCACHE_RETURN_SLOT  ((ushort)offsetof(spill_state_t, fcache_return))
 #endif
 
@@ -959,7 +959,7 @@ void arch_thread_exit(dcontext_t *dcontext _IF_WINDOWS(bool detach_stacked_callb
 void arch_thread_profile_exit(dcontext_t *dcontext);
 void arch_profile_exit(void);
 #endif
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 void arch_reset_stolen_reg(void);
 void arch_mcontext_reset_stolen_reg(dcontext_t *dcontext, priv_mcontext_t *mc);
 #endif
@@ -977,7 +977,7 @@ priv_mcontext_t *dr_mcontext_as_priv_mcontext(dr_mcontext_t *mc);
 priv_mcontext_t *get_priv_mcontext_from_dstack(dcontext_t *dcontext);
 void dr_mcontext_init(dr_mcontext_t *mc);
 void dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml);
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 reg_t get_stolen_reg_val(priv_mcontext_t *context);
 void set_stolen_reg_val(priv_mcontext_t *mc, reg_t newval);
 #endif
@@ -1462,7 +1462,7 @@ decode_init(void);
 # define MAX_PAD_SIZE 3
 
 /****************************************************************************/
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 
 # ifdef X64
 #  define FRAG_IS_THUMB(flags) false

diff --git a/core/arch/asm_defines.asm b/core/arch/asm_defines.asm
@@ -65,7 +65,7 @@
 # error ARM is only 32-bit; AARCH64 is 64-bit
 #endif
 
-#if (defined(ARM) || defined(AARCH64)) && defined(WINDOWS)
+#if defined(AARCHXX) && defined(WINDOWS)
 # error ARM/AArch64 on Windows is not supported
 #endif
 
@@ -106,7 +106,7 @@
 #  else
 #   define SYMREF(sym) [sym]
 #  endif
-# elif defined(ARM) || defined(AARCH64)
+# elif defined(AARCHXX)
 #  define BYTE /* nothing */
 #  define WORD /* nothing */
 #  define DWORD /* nothing */
@@ -307,7 +307,7 @@ ASSUME fs:_DATA @N@\
 # define PTRSZ DWORD
 #endif
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 /* ARM AArch64 calling convention:
  * SP:       stack pointer
  * x30(LR):  link register
@@ -680,7 +680,7 @@ ASSUME fs:_DATA @N@\
 # define RETURN   ret
 # define INC(reg) inc reg
 # define DEC(reg) dec reg
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 # define REG_SCRATCH0 REG_R0
 # define REG_SCRATCH1 REG_R1
 # define REG_SCRATCH2 REG_R2

diff --git a/core/arch/decode.h b/core/arch/decode.h
@@ -434,7 +434,7 @@ bool is_isa_mode_legal(dr_isa_mode_t mode);
  * Later, if needed, we can introduce a new field in dcontext_t (xref i#862).
  */
 # define X64_CACHE_MODE_DC(dc) (X64_MODE_DC(dc) IF_X64(|| DYNAMO_OPTION(x86_to_x64)))
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 # define X64_MODE_DC(dc) IF_X64_ELSE(true, false)
 # define X64_CACHE_MODE_DC(dc) IF_X64_ELSE(true, false)
 #endif

diff --git a/core/arch/emit_utils_shared.c b/core/arch/emit_utils_shared.c
@@ -792,7 +792,7 @@ coarse_indirect_stub_jmp_target(cache_pc stub)
     ASSERT(*prefix_tgt == JMP_OPCODE);
     tgt = (cache_pc) PC_RELATIVE_TARGET(prefix_tgt+1);
     return tgt;
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */
     ASSERT_NOT_IMPLEMENTED(false);
     return NULL;
@@ -3366,7 +3366,7 @@ instr_t *
 create_syscall_instr(dcontext_t *dcontext)
 {
     int method = get_syscall_method();
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
     if (method == SYSCALL_METHOD_SVC || method == SYSCALL_METHOD_UNINITIALIZED) {
         return INSTR_CREATE_svc(dcontext, opnd_create_immed_int((char)0x0, OPSZ_1));
     }
@@ -4581,7 +4581,7 @@ emit_do_syscall_common(dcontext_t *dcontext, generated_code_t *code,
     *syscall_offs += AARCH64_INSTR_SIZE;
 #endif
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
     /* We have to save r0 in case the syscall is interrupted.  We can't
      * easily do this from dispatch b/c fcache_enter clobbers some TLS slots.
      */
@@ -5145,7 +5145,7 @@ special_ibl_xfer_is_thread_private(void)
 #endif
 }
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
 size_t
 get_ibl_entry_tls_offs(dcontext_t *dcontext, cache_pc ibl_entry)
 {
@@ -5351,7 +5351,7 @@ byte *
 emit_clean_call_save(dcontext_t *dcontext, byte *pc, generated_code_t *code)
 {
     instrlist_t ilist;
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
     /* FIXME i#1551, i#1569:
      * NYI on ARM/AArch64 (no assert here, it's in get_clean_call_save())
      */

diff --git a/core/arch/instr.h b/core/arch/instr.h
@@ -257,7 +257,7 @@ typedef enum _dr_pred_type_t {
      * unconditionally written, unlike regular destination operands.
      */
     DR_PRED_COMPLEX,
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     DR_PRED_EQ, /**< ARM condition: 0000 Equal                   (Z == 1)           */
     DR_PRED_NE, /**< ARM condition: 0001 Not equal               (Z == 0)           */
     DR_PRED_CS, /**< ARM condition: 0010 Carry set               (C == 1)           */
@@ -2838,7 +2838,7 @@ enum {
     EFLAGS_ARITH = EFLAGS_CF|EFLAGS_PF|EFLAGS_AF|EFLAGS_ZF|EFLAGS_SF|EFLAGS_OF,
 };
 
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 # define EFLAGS_READ_N      0x00000001 /**< Reads N (negative flag). */
 # define EFLAGS_READ_Z      0x00000002 /**< Reads Z (zero flag). */
 # define EFLAGS_READ_C      0x00000004 /**< Reads C (carry flag). */

diff --git a/core/arch/instr_inline.h b/core/arch/instr_inline.h
@@ -154,7 +154,7 @@ opnd_is_far_rel_addr(opnd_t opnd)
     return IF_X86_ELSE(opnd.kind == REL_ADDR_kind && opnd.aux.segment != DR_REG_NULL,
                        false);
 }
-# elif defined(ARM) || defined(AARCH64)
+# elif defined(AARCHXX)
 #  ifdef ARM
 #   define OPND_IS_REL_ADDR(op) \
     ((op).kind == REL_ADDR_kind || \
@@ -258,7 +258,7 @@ opnd_create_pc(app_pc pc)
      opnd_is_immed_int(opnd), \
      "opnd_get_flags called on non-reg non-base-disp non-immed-int opnd") \
      0)
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 # define OPND_GET_FLAGS(opnd) \
     (CLIENT_ASSERT_(opnd_is_reg(opnd) || opnd_is_base_disp(opnd) || \
      opnd_is_immed_int(opnd), \
@@ -293,7 +293,7 @@ opnd_create_pc(app_pc pc)
                            opnd_is_rel_addr(opnd)), \
                     "opnd_get_segment called on invalid opnd type") \
      (opnd).aux.segment)
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
 # define OPND_GET_SEGMENT(opnd) DR_REG_NULL
 #endif
 #define opnd_get_segment OPND_GET_SEGMENT

diff --git a/core/arch/instr_shared.c b/core/arch/instr_shared.c
@@ -3129,7 +3129,7 @@ instr_raw_is_tls_spill(byte *pc, reg_id_t reg, ushort offs)
          /* 0x1e for ebx, 0x0e for ecx, 0x06 for eax */
          *(pc+2) == MODRM_BYTE(0/*mod*/, reg_get_bits(reg), 6/*rm*/) &&
          *((uint*)(pc+4)) == os_tls_offset(offs));
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */
     ASSERT_NOT_IMPLEMENTED(false);
     return false;
@@ -3168,7 +3168,7 @@ instr_check_tls_spill_restore(instr_t *instr, bool *spill, reg_id_t *reg, int *o
         opnd_is_far_base_disp(memop) &&
         opnd_get_segment(memop) == SEG_TLS &&
         opnd_is_abs_base_disp(memop)
-#elif defined (ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
         opnd_is_base_disp(memop) &&
         opnd_get_base(memop) == dr_reg_stolen &&
         opnd_get_index(memop) == DR_REG_NULL
@@ -3223,7 +3223,7 @@ instr_is_tls_xcx_spill(instr_t *instr)
                                       REG_ECX, MANGLE_XCX_SPILL_SLOT);
     } else
         return instr_is_tls_spill(instr, REG_ECX, MANGLE_XCX_SPILL_SLOT);
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */
     ASSERT_NOT_IMPLEMENTED(false);
     return false;

diff --git a/core/arch/interp.c b/core/arch/interp.c
@@ -2515,7 +2515,7 @@ bb_process_IAT_convertible_indjmp(dcontext_t *dcontext, build_bb_t *bb,
     bb->exit_target = target;
     *elide_continue = false;    /* matching, but should stop bb */
     return true;               /* matching */
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */
     ASSERT_NOT_IMPLEMENTED(false);
     return false;
@@ -2626,7 +2626,7 @@ bb_process_IAT_convertible_indcall(dcontext_t *dcontext, build_bb_t *bb,
      */
     *elide_continue = false;    /* matching, but should stop bb */
     return true;                /* converted indirect to direct */
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */
     ASSERT_NOT_IMPLEMENTED(false);
     return false;
@@ -5724,7 +5724,7 @@ instr_is_trace_cmp(dcontext_t *dcontext, instr_t *inst)
         instr_get_opcode(inst) == OP_jmp
 # endif
         ;
-#elif defined(ARM) || defined(AARCH64)
+#elif defined(AARCHXX)
     /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */
     ASSERT_NOT_IMPLEMENTED(DYNAMO_OPTION(disable_traces));
     return false;

diff --git a/core/arch/mangle_shared.c b/core/arch/mangle_shared.c
@@ -822,7 +822,7 @@ mangle(dcontext_t *dcontext, instrlist_t *ilist, uint *flags INOUT,
         }
 #endif /* X64 || ARM */
 
-#if defined(ARM) || defined(AARCH64)
+#ifdef AARCHXX
         if (!instr_is_meta(instr) && instr_reads_thread_register(instr)) {
             next_instr = mangle_reads_thread_register(dcontext, ilist,
                                                       instr, next_instr);