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[drcachesim] Record the cpu along with the timestamp and include in the final trace #2843

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derekbruening opened this issue Feb 21, 2018 · 1 comment
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[drcachesim] Record the cpu along with the timestamp and include in the final trace #2843

derekbruening opened this issue Feb 21, 2018 · 1 comment
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Component-DrMemtrace Component-DRTool Type-Feature

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@derekbruening
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Offline traces today record a timestamp per thread buffer output, though it's used during post-processing and then discarded. This is a request to include it in the final trace (and add it for online traces), and to add the current cpu to the timestamp, to provide an approximation of which hardware threads were in use.
@derekbruening derekbruening self-assigned this Feb 21, 2018
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Once the cpu markers are in the trace, we should change the cache simulator to schedule threads to cores based on the markers: map actual cpu id's to cores and then send each thread buffer to its indicated core.

derekbruening added a commit that referenced this issue Feb 23, 2018
@derekbruening
i#2843 trace cpus: add cpu and timestamp trace markers
761d5d5 
Adds a timestamp marker and a cpu marker to the trace buffer header for
each thread's buffer unit output.  The timestamp was already in the raw
offline trace format, but now it is in the final trace for both offline and
online as a new marker type.  The cpu is completely new and specifies which
core that thread executed on at the granularity of the buffer unit.

Refactors the initial and per-output buffer headers to fix warts in the
tracer: now the initial buffer's timestamp is from output time rather than
thread init time; the initial header is more cleanly skipped for virt2phys;
header uses are more normalized and easier to understand.

Updates the basic_counts tool to separate these new scheduling marks from
kernel transfer and other markers.  Updates the corresponding
documentation.

A forthcoming change will update the cache simulator to schedule threads
based on executed cores rather than a thread round-robin scheme.

Issue: #2843
@derekbruening derekbruening mentioned this issue Feb 23, 2018
Merged
derekbruening added a commit that referenced this issue Feb 24, 2018
@derekbruening
i#2843 trace cpus: add cpu and timestamp trace markers (#2849)
aedf9be 
Adds a timestamp marker and a cpu marker to the trace buffer header for
each thread's buffer unit output.  The timestamp was already in the raw
offline trace format, but now it is in the final trace for both offline and
online as a new marker type.  The cpu is completely new and specifies which
core that thread executed on at the granularity of the buffer unit.

Refactors the initial and per-output buffer headers to fix warts in the
tracer: now the initial buffer's timestamp is from output time rather than
thread init time; the initial header is more cleanly skipped for virt2phys;
header uses are more normalized and easier to understand.

Updates the basic_counts tool to separate these new scheduling marks from
kernel transfer and other markers.  Updates the corresponding
documentation.

A forthcoming change will update the cache simulator to schedule threads
based on executed cores rather than a thread round-robin scheme.

Issue: #2843
derekbruening added a commit that referenced this issue Feb 26, 2018
@derekbruening
i#2843 trace cpus: simulate according to traced cpu mappings
ce4c496 
Changes the default thread scheduling on simulated cores to match the new
recorded cpu mappings.  The cpu's are assigned to cores in a round-robin
fashion, and each thread region is assigned to the core that owns the cpu
in the thread region's header markers.

Adds a new option -static_scheduling which requests the old method, where
the cpu markers are ignored and threads are statically assigned to cores.

To keep tests deterministic, they are run with -static_scheduling by
default.  The tests with many threads which need to match any core mapping
anyway override that to test the cpu scheduling.

Updates the documentation for the new CPU-scheduling default.

Fixes #2843
@derekbruening derekbruening mentioned this issue Feb 26, 2018
Merged
derekbruening added a commit that referenced this issue Feb 26, 2018
@derekbruening
i#2843 trace cpus: simulate according to traced cpu mappings (#2853)
a51325f 
Adds a new option -cpu_scheduling which schedules trace execution on
simulated cores to match the new recorded cpu mappings.  The cpu's are
assigned to cores in a round-robin fashion, and each thread region is assigned
to the core that owns the cpu in the thread region's header markers.

Adds -cpu_scheduling to several tests with multiple threads.

Adds the documentation for the new option.

Fixes #2843
derekbruening added a commit that referenced this issue Feb 27, 2018
@derekbruening
i#2843 trace cpus: support legacy headers
3167e1e 
The trace header refactoring in aedf9be broke post-processing of legacy
trace headers where the first timestamp precedes the first thread id.  We
fix that here.

Issue: #2843
@derekbruening derekbruening mentioned this issue Feb 27, 2018
Merged
derekbruening added a commit that referenced this issue Feb 27, 2018
@derekbruening
i#2843 trace cpus: support legacy headers (#2854)
b6baa11 
The trace header refactoring in aedf9be broke post-processing of legacy
trace headers where the first timestamp precedes the first thread id.  We
fix that here.

Issue: #2843
derekbruening added a commit that referenced this issue May 29, 2018
@derekbruening
i#2638 core sim: document several recent features
441b065 
Adds documentation for several recent features geared toward core
simulator support: avoiding thread switch gaps after branches; cpu
markers; kernel xfer markers; and the raw2trace mapping interfaces.

Issue: #2638, #2843, #2708, #2006
@derekbruening derekbruening mentioned this issue May 29, 2018
Merged
derekbruening added a commit that referenced this issue May 29, 2018
@derekbruening
i#2638 core sim: document several recent features (#3035)
ce6b0fc 
Adds documentation for several recent features geared toward core
simulator support: avoiding thread switch gaps after branches; cpu
markers; kernel xfer markers; and the raw2trace mapping interfaces.

Issue: #2638, #2843, #2708, #2006
fhahn pushed a commit that referenced this issue Jun 18, 2018
@derekbruening @fhahn
i#2638 core sim: document several recent features (#3035)
b0a8936 
Adds documentation for several recent features geared toward core
simulator support: avoiding thread switch gaps after branches; cpu
markers; kernel xfer markers; and the raw2trace mapping interfaces.

Issue: #2638, #2843, #2708, #2006
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